Read Sharp SD-NX10 (serv.man10) Service Manual online
SD-NX10H
– 78 –
WAVEFORMS OF 1-BIT CIRCUIT
T
2
1
2.00V/div
500ns/div
194.545465
µ
s
520mV
2.00V/div
AD IC Output
+ Side
- Side
5V
Amplitude
from 0 to 5 V
from 0 to 5 V
1
2
2
2
1
2.00V/div
500ns/div
194.545465
µ
s
-12.30V
2.00V/div
AD IC NF IN
In partial pressure OUT, 4 to 7 V amplitude
of GND reference is observed.
In IC of 75 kohms, the reference is 2.5 V
because of VREF. Due to imaginary GND
of operational amplifier inside IC, the
waveform cannot be monitored.
This waveform is partial pressure OUT.
of GND reference is observed.
In IC of 75 kohms, the reference is 2.5 V
because of VREF. Due to imaginary GND
of operational amplifier inside IC, the
waveform cannot be monitored.
This waveform is partial pressure OUT.
3
4
T
2.00V/div
50.0ns/div
0.0s
-12.30V
2.00V/div
LEVEL SHIFT OUT
DEAD TIME
ZOOM UP
Dead time is generated by level
shift input.
Leading edge is delayed at CR,
passing R at DI.
Set value: 20 -25 nsec
shift input.
Leading edge is delayed at CR,
passing R at DI.
Set value: 20 -25 nsec
5
6
6
T
2.00V/div
500ns/div
194.545465
µ
s
-12.47V
2.00V/div
| @
POWER SUPPLY
LEVEL SHIFT OUT
5V
Waveform after level shift
On the reference side, 5 V amplitude
is observed at + 2 V (negative supply
voltage), corresponding to VINH and
VINL of gate driver during 9 V operation.
(Approx. 0.8 VCC and 0.2 VSS)
On the reference side, 5 V amplitude
is observed at + 2 V (negative supply
voltage), corresponding to VINH and
VINL of gate driver during 9 V operation.
(Approx. 0.8 VCC and 0.2 VSS)
7
8
8
FET is based on the negative
supply voltage; the gate voltage
of the LOW side FET operates
with the negative power and + 9 V.
supply voltage; the gate voltage
of the LOW side FET operates
with the negative power and + 9 V.
To make HIGH SIDE FET
completely on, the positive
supply voltage of + 4.5 V or over
is required. At the bootstrap, the
gate drive voltage is generated;
the HIGH side is driven between
(positive power) + 6 V and the
negative power.
completely on, the positive
supply voltage of + 4.5 V or over
is required. At the bootstrap, the
gate drive voltage is generated;
the HIGH side is driven between
(positive power) + 6 V and the
negative power.
T
2
1
10.0V/div
500ns/div
194.545465
µ
s
-12.3V
10.0V/div
HIGH SIDE OUT
LOW SIDE OUT
GATE DRIVE OUT
9
10
T
10.0V/div
500ns/div
194.545465
µ
s
-12.3V
10.0V/div
+SIDE
+FETOUT
- SIDE
Waveforms before low-pass filters at both
ends of the speaker
H-bridge may be considered as BTL.
However, here and at the gate drive, dead
time is not observed; since bootstrap
operates based on output, DEAD TIME
part is in floating condition. The waveform
on the HI GH side shows that only the
booted voltage lowers.
ends of the speaker
H-bridge may be considered as BTL.
However, here and at the gate drive, dead
time is not observed; since bootstrap
operates based on output, DEAD TIME
part is in floating condition. The waveform
on the HI GH side shows that only the
booted voltage lowers.
2
1
11
12
12
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