Read Sharp SD-EX200 (serv.man18) Service Manual online
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SD-EX200H
IC101 VHiCS4340KS-1: DAC IC (CS4340KS) (1/2)
1
RST
Input
Reset
The device enters a low power mode and all internal state machines are reset to the default
settings when low. RST should be held low during power-up until the power supply, master
and left/right clocks are stable.
The device enters a low power mode and all internal state machines are reset to the default
settings when low. RST should be held low during power-up until the power supply, master
and left/right clocks are stable.
2
SDATA
Input
Serial Audio Data
Two's complement MSB-first serial data is input on this pin. The data is clocked into SDATA
via the serial clock and the channel is determined by the Left/Right clock.
The required relationship between the Left/Right clock, serial clock and serial data is defined
by the DIF1-0 pins.
Two's complement MSB-first serial data is input on this pin. The data is clocked into SDATA
via the serial clock and the channel is determined by the Left/Right clock.
The required relationship between the Left/Right clock, serial clock and serial data is defined
by the DIF1-0 pins.
3
SCLK
Input
Serial Clock
Clocks the individual bits of the serial data into the SDATA pin.
The required relationship between the Left/Right clock, serial clock and serial data is defined
by the DIF1-0 pins.
The CS4340 supports both internal and external serial clock generation modes.
Internal SCLK mode is used to gain access to extra de-emphasis modes.
Internal Serial Clock Mode
In the internal Serial Clock Mode, the serial clock is internally derived and synchronous with
the master clock and left/right clock.
The SCLK/LRCK frequency ratio is either 32, 48 or 64 depending upon the DIF1-0 pins.
Operation in this mode is identical to operation with an external serial clock synchronized with
LRCK.
External Serial Clock Mode
The CS4340 will enter the External Serial Clock Mode whenever 16 low to high transitions
are detected on the SCLK pin during any phase of the LRCK period.
The device will revert to Internal Serial Clock Mode if no low to high transitions are detected
on the SCLK pin for 2 consecutive periods of LRCK.
Clocks the individual bits of the serial data into the SDATA pin.
The required relationship between the Left/Right clock, serial clock and serial data is defined
by the DIF1-0 pins.
The CS4340 supports both internal and external serial clock generation modes.
Internal SCLK mode is used to gain access to extra de-emphasis modes.
Internal Serial Clock Mode
In the internal Serial Clock Mode, the serial clock is internally derived and synchronous with
the master clock and left/right clock.
The SCLK/LRCK frequency ratio is either 32, 48 or 64 depending upon the DIF1-0 pins.
Operation in this mode is identical to operation with an external serial clock synchronized with
LRCK.
External Serial Clock Mode
The CS4340 will enter the External Serial Clock Mode whenever 16 low to high transitions
are detected on the SCLK pin during any phase of the LRCK period.
The device will revert to Internal Serial Clock Mode if no low to high transitions are detected
on the SCLK pin for 2 consecutive periods of LRCK.
DEM1
Input
De-emphasis Control
Implementation of the standard 15
Implementation of the standard 15
µ
s/50
µ
s digital de-enphasis filter response, required
reconfiguration of the digital filter to maintain the proper filter response for 32, 44.1 or 48 kHz
sample rates.
When using Internal Serial Clock Mode, as described above, Pin 3 is available for de-emphasis
control, DEM1, and all de-enphasis filters are available.
When using External Serial Clock Mode, as described above, Pin 3 is not available for
de-emphasis use and only the 44.1 kHz de-emphasis filter is available.
Note: De-emphasis is not available in High-Rate Mode.
sample rates.
When using Internal Serial Clock Mode, as described above, Pin 3 is available for de-emphasis
control, DEM1, and all de-enphasis filters are available.
When using External Serial Clock Mode, as described above, Pin 3 is not available for
de-emphasis use and only the 44.1 kHz de-emphasis filter is available.
Note: De-emphasis is not available in High-Rate Mode.
4
LRCK
Input
Left/Right Clock
The Left/Right clock determines which channel is currently being input on the serial audio
data input, SDATA. The frequency of the Left/Right clock must be at the input sample rate.
Audio samples in Left/Right sample pairs will be simultaneously output from the digital- to-
analog converter whereas Right/Left pairs will exhibit a one sample period difference.
The required relationship between the Left/Right clock, serial clock and serial data is defined
by the DIF1-0 pins.
The Left/Right clock determines which channel is currently being input on the serial audio
data input, SDATA. The frequency of the Left/Right clock must be at the input sample rate.
Audio samples in Left/Right sample pairs will be simultaneously output from the digital- to-
analog converter whereas Right/Left pairs will exhibit a one sample period difference.
The required relationship between the Left/Right clock, serial clock and serial data is defined
by the DIF1-0 pins.
5
MCLK
Input
Master Clock
The master clock frequency must be either 256x, 384x or 512x the input sample rate in Base
Rate Mode (BRM) and either 128x or 129x the input sample rate in High Rate Mode (HRM).
The master clock frequency must be either 256x, 384x or 512x the input sample rate in Base
Rate Mode (BRM) and either 128x or 129x the input sample rate in High Rate Mode (HRM).
Pin No.
Port Name
Input/Output
Function
Sample
Rate
(kHz)
MCLK (MHz)
HRM
BRM
128x
192x
256x
384x
512x
32
4.0960
6.1440
8.1920
12.2880
16.3840
44.1
5.6448
8.4672
11.2896
16.9344
22.5792
48
6.1440
9.2160
12.2880
18.4320
24.5760
64
8.1920
12.2880
—
—
—
88.2
11.2896
16.9344
—
—
—
96
12.2880
18.4320
—
—
—
Common Master Clock Frequencies
DEM1
DESCRIPTION
0
Disabled
0
44.1 kHz
1
48 kHz
1
32 kHz
Internal Serial Clock Mode
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