Read Sharp SD-AT50H (serv.man9) Service Manual online
– 9 –
SD-AT50H
Figure 9-4
ADJUSTMENT
Figure 9-3 OUTPUT OFFSET LEVEL
1-bit amplifier's output offset voltage adjustment
Adjust VRA100, VRA101, VRA200, VRA201, VRA300 and
VRA301 so that the DC voltage between speaker terminals +
and - is set to 0
VRA301 so that the DC voltage between speaker terminals +
and - is set to 0
±
5 mV at AC 230 V.
Electronic
Voltage
SO801
AC 230 V
Set
Output:
SpeakerTerminal
SpeakerTerminal
+
-
VR : 0
Input : AUX
Input : AUX
5
3
1
6
4
2
R-CH Output Offset Adjusument
L-CH Output Offset Adjusument
VRA300
VRA200
VRA100
VRA301
VRA201
VRA101
DESCRIPTION OF CIRCUIT FOR 1-BIT UNIT
(SEE THE WIRING DIAGRAMS ON PAGES 38 AND 39.)
Input section
Signals from CNA100 are coupled by CA100, CA101, CA200,
CA300 and CA301, and then sent into the A/D converter IC
(ICA100, ICA200, ICA300).
Signals from CNA100 are coupled by CA100, CA101, CA200,
CA300 and CA301, and then sent into the A/D converter IC
(ICA100, ICA200, ICA300).
modulation 1-bit converter
Signals from the A/D converter IC (ICA100, ICA200, ICA300)
are converted to 1-bit signals and sent differentially. Refer to
the technical manual of SM-SX100 for the details of conversion
to 1-bit signals.
Signals from the A/D converter IC (ICA100, ICA200, ICA300)
are converted to 1-bit signals and sent differentially. Refer to
the technical manual of SM-SX100 for the details of conversion
to 1-bit signals.
Dead time and level shift
As for the waveform of 1-bit signals sent through the A/D
converter IC (ICA100, ICA200, ICA300), its rise time is delayed
by 20 nsec ~ 25 nsec compared to the fall time due to RA114
~ RA117, RA214 ~ RA217, RA314 ~ RA317 and CA106 ~
CA109, CA206 ~ CA209, CA306 ~ CA309 and DA104 ~
DA107, and DA304 ~ DA307. This is for reducing loss of the
switching circuit described later. The 1-bit signals are sent into
the buffer IC (the AND gate IC) (ICA101, ICA201, ICA301) and
sent as the shaped waveform.
As for the waveform of 1-bit signals sent through the A/D
converter IC (ICA100, ICA200, ICA300), its rise time is delayed
by 20 nsec ~ 25 nsec compared to the fall time due to RA114
~ RA117, RA214 ~ RA217, RA314 ~ RA317 and CA106 ~
CA109, CA206 ~ CA209, CA306 ~ CA309 and DA104 ~
DA107, and DA304 ~ DA307. This is for reducing loss of the
switching circuit described later. The 1-bit signals are sent into
the buffer IC (the AND gate IC) (ICA101, ICA201, ICA301) and
sent as the shaped waveform.
Low pass filter circuit
1-bit signals switched by the output IC (ICA102, ICA107,
ICA302 and ICA307) are converted to analog signals through
the lowpass filter consisting of LA104 ~ LA107, LA204 ~
LA207, LA304 ~ LA307 and CA114 ~ CA117, CA214 ~
CA217, and CA314 ~ CA317. The low pass filter functions
when a frequency exceeds 20 kHz, and reduces it by approx.
3 dB when it reaches approx. 40 kHz.
1-bit signals switched by the output IC (ICA102, ICA107,
ICA302 and ICA307) are converted to analog signals through
the lowpass filter consisting of LA104 ~ LA107, LA204 ~
LA207, LA304 ~ LA307 and CA114 ~ CA117, CA214 ~
CA217, and CA314 ~ CA317. The low pass filter functions
when a frequency exceeds 20 kHz, and reduces it by approx.
3 dB when it reaches approx. 40 kHz.
Dynamic feedback circuit
The 1-bit signals switched by the output IC (ICA102, ICA107,
ICA 302 and ICA307) oscillate between positive and negative
voltage. After resistance-division, the signals are fed back to
the A/D converter IC (ICA100, ICA200, ICA300) through NF
resistance 75 kohms (RA130 ~ RA133, RA230 ~ RA233,
RA330 ~ RA333). The peak-to-peak voltage reaches approx.
5 V.
The 1-bit signals switched by the output IC (ICA102, ICA107,
ICA 302 and ICA307) oscillate between positive and negative
voltage. After resistance-division, the signals are fed back to
the A/D converter IC (ICA100, ICA200, ICA300) through NF
resistance 75 kohms (RA130 ~ RA133, RA230 ~ RA233,
RA330 ~ RA333). The peak-to-peak voltage reaches approx.
5 V.
Display
