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SD-AT1000
– 12 –
Figure 12 BLOCK DIAGRAM (1/10)
+12V
+12V
A_+9V
A_+9V
80
79
78
77
77
76
75
70
67
38
37
36
35
32
29
28
27
26
25
5 6 7 8
4 3
1
4 3 2
1
5 6
7 8
24 23 22 21
19
17
8
9
10
11
13
14
15
16
1
2
3
4
7
48 49 50 51 52 53 54 55
57
41
44 45 46 47
P_CONT_LEVEL
LINE3_LCH
LINE3_RCH
LINE1_RCH
LINE2_RCH
LINE2_LCH
LINE1_LCH
OUT_L
CONFIG
+B_CHECK
UCON5V
RIN
LIN
LOUT2
ROUT2
LOUT1
ROUT1
ROUT3
LOUT3
H.P_SW
CONFIG
CCB_DI
CCB_CL
CCB_DO
CCB_CE
FUN_LOCK
BASS_SW
VOL_CL
VOL_DA
OFFSETPROTECT
A/D_RESET
S_MUTE
S_S_MUTE
C_S_MUTE
F_S_MUTE
W_S_MUTE
L_MUTE
OUTSR_RCH
OUTC
OUTSW
OUTSR_LCH
S_MUTE
MON_OUTR
MON_OUTL
OUT_R
VOL_CL
VOL_DA
TUN_L
TUN_R
PROTECT
PROTECT
9V
LINE1 OUT
D_+5V
L_
SW
LINE 2
LINE 1 IN
LINE 3
R-CH
L-CH
L-CH
R-CH
R-CH
L-CH
L-CH
R-CH
CENTER
GND(U-COM)
AGND2
AGND1
IN DSPSL
INDSPC
IN DSPSW
OUTSL
OUTSR
OUTSW
OUTC
IN2DSP
OUT1(+)
IN DVDSR
VCC
DA
IN1MIX
CL
MUTE
OUT2(+)
INDVD SW
AGND5
AGND6
VEE
AGND4
DGND
IN1DSP
INDVDC
IN DVDSL
AGND8
IN81
IN72
IN71
IN62
OUT2
OUT1
IN61
IN41
IN42
IN32
IN21
AGND9
IN12
IN11
IN11
ROUT32
ROUT31
ROUT31
AGND10
AGND3
AGND7
IN22
IN DSPSR
IN2MIX
IN31
14
16
15
17
18
20
13
19
21
22
12
11
11
10
7
23
8
9
24
6
4
5
3
2
2
1
25
26
27
R_CH
L_CH
H.P SW
D_GND
A_GND
PROTECT
D_+5V
D_GND
L-CH
H.P SW
A_GND
R-CH
1
3
4
5
5
6
1
2
3
4
4
5
1
2
3
4
4
5
A_+9V
VDD
VSS
+
+
–
–
+
–
VDD
–
+
VSS
3
4
5
6
7
8
9
10
13
11
1
CNP701
TO DISPLAY PWB
TO DSP SECTION
TO DSP SECTION
TO DSP SECTION
+B
BI601
CNS601
JT501
LINE1 INPUT/
OUTPUT TERMINAL
JT502
LINE2/LINE3
INPUT TERMINAL
Q528
Q501
Q532
Q533
Q531
Q504
Q503
Q599
Q598
Q502
IC520
TJM4558CD
OPE AMP.
IC505
NJM4565M
BUFFER AMP.
CNP501
IC501
BD3811K1
VOLUME IC
D538
D537
CNP601
JK1
HEADPHONES
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