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SD-AT100H
– 86 –
Figure 86 SCHEMATIC DIAGRAM (15/23)
A
B
C
D
E
F
G
H
1
2
3
4
5
6
• NOTES ON SCHEMATIC DIAGRAM can be found on page 96.
FM SIGNAL
1-BIT AMP. PWB-F1/2/3
9
5
10
13
12
14
4
2
1
9
10
11
12
13 14 15 16 17
18 19 20
21
22 23 24
8
1
2
3
4
5
6
7
3
2
1
3
2
1
5
4
3
2
1
5
4
3
2
1
5
4
3
2
1
D+5V
A+5V
–B_DRIVER
AGND_AD
D+5V
D+5V
L_CH
R_CH
ANALOG IN L-CH
ANALOG IN R-CH
RESET
D+5V
DGND_AD
AGND_AD
A+5V
AGND
L-CH_IN
R-CH_IN
P73 12 - E
TO MAIN PWB
MCK
GNDX
XO
XI
VDDX
VDDR
OUTR(+)
OUTR(–)
OUTL(–)
OUTL(+)
GNDD
VDDL
VDA
RESET
L-CH IN
R-CH IN
R-CH Vref
L-CH Vref
GNDA
NFR2(–)
NFL1(+)
NFL2(–)
NFR1(+)
TEST
3
2
1
1
3
2
1
1
1
2
2
3
1
2
2
3
ICA100
IX2815AF
CNW508B/C/D
P77 12 - B, 12 - C TO DISPLAY PWB
CNPE01/02/03
+B
+B
+B
+B
+B
+B
+B
+B
-B
L-CH OUTPUT
OFFSET
ADJUSTMENT
R-CH OUTPUT
OFFSET
ADJUSTMENT
BIA106A/B/C
CNSA106A/B/C
CA211
0.1
LFA01
LFA02
CA288
0.1
CA196
47/25
CA289
0.1
RA153
1K
CNPA112A/B/C
CNSA112A/C/E
CNSA112B/D/F
CA197
47/25
RA100
3.3K
DA127
1SS361
DA126
1SS361
RA173
8.2K
CA109
10/10
RA102
20K
RA154
1.5K
ZDA110
MA8051M
CA194
47/16
RA182
120K
VRA100
4.7K
RA181
120K
RA178
100
RA180
390
RA179
390
RA177
100
RA175
2.2K
DA128
1SS361
DA129
1SS361
RA174
8.2K
RA101
3.3K
CA182
0.1
CXA100
11.2896MHz
CA184
47/10
CA102
0.1
CA185
0.001
CA100
18P(CH)
CA101
18P(CH)
CA103
0.1
ICA100
IX2815AF
7TH ORDER
∆∑
MODULAT
CONVERSION LSI
RA183
120K
VRA101
4.7K
RA184
120K
RA103
20K
CA108
10/10
CA105
10/10
CA106
10/10
CA189 0.001
CA188
0.001
CA186 47/10
CA107 0.1
CA187 0.001
RA104 75K
RA105 75K
RA108 75K
RA109 75K
RA202
1K
RA124
100
DA103
KDS160
RA123
100
RA115
2.2K
CA104
0.1
CA152
12P(CH)
RA112
2.2K
RA121
100
DA102
KDS160
DA100
KDS160
CA153
18P(CH)
RA113
2.2K
CA154
18P(CH)
RA114
2.2KDA101
KDS160
ICA110
74AC8F
QUAD 2 INPUT AND G
CA2
100/
CA110
0.1
CA155
12P(CH)
RA122
100
CA181
100P
(CH)
CA286
0.1
CA287
0.1
CA164
100/10
CA165
100/10
RA176
2.2K
1
3
4
2
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