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HT-SB30
5 – 3
IC406 VHiTAS3152P-1 : SMART IC - I
2
C MODE (1/1)
Pin description
Note : I - Input, O - Output
Note : I - Input, O - Output
TAS3152 (top view)
TERMINAL
I/O
DESCRIPTION
NAME
PIN
DVDD
1
-
Digital power supply, 3.3 V or 1.8 V
OSVDD
2
-
Oscillator power supply, 3.3 V
OSGND
3
-
Oscillator ground
OSGND1
4
-
Oscillator ground 1
OSGND2
5
-
Oscillator ground 2
PLVDD
6
-
PLL power supply, 3.3 V
PLGND
7
-
PLL ground
SDA
8
I/O
Input data for I
2
C
(1)
SCL
9
I
Input clock for I2C
(2)
GPIO5
10
I/O
General purpose digital input and output port
(3)
GPIO4
11
I/O
General purpose digital input and output port
(3)
GPIO3
12
I/O
General purpose digital input and output port
(3)
ADR2
13
I/O
2nd LSB address select bit for I
2
C
MODE1
14
I
Mode control selection pin
(2)
MODE1=Low, MODE2=Low : Reserved
MODE1=Low, MODE2=High : I
MODE1=Low, MODE2=High : I
2
C mode
MODE2
15
I
MODE1=High : SPI mode, MODE2 pin changes MS pin (chip select for
SPI)
SPI)
GPIO6
19xxxxxx
I/O
General purpose digital input and output port
SCK
17
I
System clock input
(2)
BCK
18
I/O
Audio data bit clock input (slave) or output (master)
(2)
DIN
19
I
Audio data input
(2)
LRCK
20
I/O
Audio data word clock input (slave) or output (master)
(2)
ADR1
21
I
LSB address select bit for I
2
C
XSMT
22
I
Soft mute control
(2)
Softmute (Low) / soft un-mute (High)
LDOO
23
-
Internal logic supply rail terminal for decoupling, 1.8 V
DGND
24
-
Digital ground
(1)
Open-drain configuration in out mode.
(2)
Failsafe LVCMOS Schmitt trigger input.
(3)
Internal Pulldown in SPI Mode
TAS3152
1 DVDD
2 O
S
VDD
3
O
S
GND
4 O
S
GND1
5 O
S
GND2
6 PLVDD
7 PLGND
8
S
DA
9
S
CL
10 GPIO5
11 GPIO4
12 GPIO
3
DGND 24
LDOO 2
3
X
S
MT 22
ADR1 21
LRCK 20
DIN 19
BCK 18
S
CK 17
GPIO6 16
MODE2 15
MODE1 14
ADR2 1
3
Figure 5-2: Block diagram of IC
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