Read Sharp HT-DV40H (serv.man4) Service Manual online
HT-DV40H
8 – 34
D12
29
LVTTL
B
RGB24 interface bit-12 (B[2]) or GPIO_1_12(CCIR656-like link)
D13
28
LVTTL
B
RGB24 interface bit-13 (B[3]) or GPIO_1_13(CCIR656-like link)
D14
27
LVTTL
B
RGB24 interface bit-14 (B[4]) or GPIO_1_14(CCIR656-like link)
D15
26
LVTTL
B
RGB24 interface bit-15 (B[5]) or GPIO_1_15(CCIR656-like link)
D16
23
LVTTL
Intput
RGB24 interface bit-16 (B[6]) or CCIR656-like bit-0/ CCIR656-like bit-7
D17
22
LVTTL
Intput
RGB24 interface bit-17 (B[7]) or CCIR656-like bit-1/ CCIR656-like bit-6
D18
21
LVTTL
Intput
RGB24 interface bit-18 (R[0]) or CCIR656-like bit-2/ CCIR656-like bit-5
D19
20
LVTTL
Intput
RGB24 interface bit-19 (R[1]) or CCIR656-like bit-3/ CCIR656-like bit-4
D20
19
LVTTL
Intput
RGB24 interface bit-20 (G[0]) or CCIR656-like bit-4/ CCIR656-like bit-3
D21
18
LVTTL
Intput
RGB24 interface bit-21 (G[1]) or CCIR656-like bit-5/ CCIR656-like bit-2
D22
17
LVTTL
Intput
RGB24 interface bit-22 (B[0]) or CCIR656-like bit-6/ CCIR656-like bit-1
D23
16
LVTTL
Intput
RGB24 interface bit-23 {B[1]} or CCIR656-like bit-7/ CCIR656-like bit-0
IHS
119
LVTTL
Intput
RGB24 interface HSYNC
IVS
118
LVTTL
Intput
RGB24 interface VSYNC
Analog Video Output Interface ñ DAC
DAC0
97
Analog
Output
DAC analog red / Y output
DAC1
96
Analog
Output
DAC analog green / Pb output
DAC2
93
Analog
Output
DAC analog blue / Pr output
AHS
90
LVTTL
Output
Separate HSYNC signal (digital output)
AVS
89
LVTTL
Output
Separate VSYNC signal (digital output)
Audio Interface
MCLK
2
LVTTL
Intput
Audio input Master Clock
(The supplied clock must be ìcoherentî with the input S/PDIF or I
(The supplied clock must be ìcoherentî with the input S/PDIF or I
2
S)
S/PDIF
9
LVTTL
Intput
S/PDIF audio input
SCK
3
LVTTL
Intput
I
2
S Serial Clock
WS
4
LVTTL
Intput
I
2
S Word Select
SD0
8
LVTTL
Intput
I
2
S Serial Data 0
SD1
7
LVTTL
Intput
I
2
S Serial Data 1
SD2
6
LVTTL
Intput
I
2
S Serial Data 2
SD3
5
LVTTL
Intput
I
2
S Serial Data 3
HDMI Interface
TX0+
73
Analog
Output
TMDS output data pairs
TX0-
72
Analog
Output
TX1+
76
Analog
Output
TMDS output data pairs
TX1-
75
Analog
Output
TX2+
79
Analog
Output
TMDS output data pairs
TX2-
78
Analog
Output
TXC+
70
Analog
Output
TMDS output clock pairs
TXC-
69
Analog
Output
HPD
48
LVTTL
Intput
Hot Plug Detect input
INT
108
LVTTL
Output
Interrupt output
DSCL
50
Schmitt
Output
DDC I2C Master Clock
DSDA
49
Schmitt
B
DDC I2C Master Data (Open drain output)
GPIO
GPIO_2_0
110
LVTTL
B
General-purpose Intput/Output
GPIO_2_1
111
LVTTL
B
General-purpose Intput/Output
GPIO_2_2
112
LVTTL
B
General-purpose Intput/Output
GPIO_2_3
88
LVTTL
B
General-purpose Intput/Output
External EEPROM Interface (I2C Address : A0)
KWP / NC
46
LVTTL
Output
Write Protect (NC for SPHE6500P/SPHE6502P)
KSCL / NC
45
LVTTL
Output
External EEPROM I2C Clock (NC for SPHE6500P/SPHE6502P)
KSDA / NC
44
LVTTL
B
External EEPROM I2C Data (NC for SPHE6500P/SPHE6502P)
Power Ground Pins
DVCC18
14,51,92,11
4,121,54,56,
58,62,64
Power
Digital power 1.8V
DGND
24,52,85,
109,120,10,
15,34,86,
107,123,57,
53,55,59,61,
63
Gnd
Digital GND
DVCC33
12,25,
43,91,115,
126,60
Power
Digital power 3.3V
HAVCC
71,77
Power
HDMI analog power 3.3V
HAGND
68,74,80,65,
82,83
Gnd
HDMI analog GND
Mnemonic
Pin#
Type
Dir.
Description
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