Read Sharp HT-DV40H (serv.man4) Service Manual online
HT-DV40H
8 – 21
M_A[12]/GPIO
174
Input/Output
SDRAM address bus [12] or GPIO[49]
R_A10
175
Output
ROM / SRAM / flash address bus bit [10]
R_A9
176
Output
ROM / SRAM / flash address bus bit [9]
R_A8
178
Output
ROM / SRAM / flash address bus bit [8]
R_A7
179
Output
ROM / SRAM / flash address bus bit [7]
R_A6
180
Output
ROM / SRAM / flash address bus bit [6]
R_A5
181
Output
ROM / SRAM / flash address bus bit [5]
R_A4
183
Output
ROM / SRAM / flash address bus bit [4]
R_A3
184
Output
ROM / SRAM / flash address bus bit [3]
R_A2
185
Output
ROM / SRAM / flash address bus bit [2]
R_A1
186
Output
ROM / SRAM / flash address bus bit [1]
AIN/AIN_L
(8202A only)
(8202A only)
187
A
(8202A only)
ADC input (left channel, with OP)
ADC input (left channel, with OP)
GPIO
(8202A-256 only)
(8202A-256 only)
187
Input/Output
GPIO
ATO
(8202A only)
(8202A only)
188
A
ADC OP output. When not used, connect a 0.1uF to ground.
GPIO
(8202A-256 only)
(8202A-256 only)
188
Input/Output
GPIO
Symbol
Pin #
Input/Output
Description
Priority selection
Function
Dir
sft_cfg1[5]=1’b1
SDRAM address bus [12]
(default)
Output
gpio_first[3][1] = 1
GPIO[49]
Input/Output
sft_cfg13[3:0] = 4'b1100
IEC_RX
Input
sft_cfg13[8:4] = 5'b10000
ADC_DATA
Input
sft_cfg13[11:9] = 3'b100
AT_DMARQ
Input
sft_cfg13[14:12] = 3'b010
AT_D[12]
Input/Output
sft_cfg13[14:12] = 3'b111
AT_D[0]
Input/Output
sft_cfg3[15:14] = 2
IOCHRDY
Input
sft_cfg7[11:8] = 4'b1000
VGA_CLK
Input
sft_cfg0[13:12] = 1
TV_LCD_DCLK
Output
sft_cfg0[13:12] = 2
TV_LCD_DCLK
Output
sfg_cfg16[3:0] = 4'b0001
FM_GPIOB[8]
Input/Output
sfg_cfg17[3:0] = 4'b0100
FM_GPIOB[19]
Input/Output
sft_cfg7[15:14] = 1
CLK27_OUT
Output
sft_cfg7[13:12] = 1
CLK54_OUT
Output
sft_cfg18[5:4] = 1
CLK48_OUT
Output
sft_cfg18[7:6] = 1
CLK108_OUT
Output
(other)
GPIO[49]
Input/Output
Priority selection
Function
Dir
gpio_first[6][5] = 1
GPIO[101]
Input/Output
sft_cfg13[8:4] = 5'b11011
ADC_DATA
Input
sft_cfg13[14:12] = 3'b111
AT_D[9]
Input/Output
sft_cfg14[10:8] = 3'b111
TV_HSYNC_SRGB
Output
sft_cfg11[5:3] = 3'b111
TS_DATA[0]
Input/Output
sft_cfg7[11:8] = 4'b1011
VGA_CLK
Input
sft_cfg13[14:12] = 3'b111
AT_D[0]
Input/Output
sft_cfg3[15:14] = 2
IOCHRDY
Input
sft_cfg7[11:8] = 4'b1000
VGA_CLK
Input
sft_cfg11[11:9] = 3'b010
TV_LCD_R_EXT[0]
Output
(other)
GPIO[101] (default)
Input/Output
Priority selection
Function
Dir
gpio_first[6][6] = 1
GPIO[102]
Input/Output
sft_cfg13[8:4] = 5'b11100
ADC_DATA
Input
sft_cfg13[14:12] = 3'b111
AT_D[6]
Input/Output
sft_cfg14[10:8] = 3'b111
TV_VSYNC_SRGB
Output
sft_cfg11[5:3] = 3'b111
EXT_TS_CLK
Input
sft_cfg11[11:9] = 3'b010
TV_LCD_R_EXT[1]
Output
(other)
GPIO[102] (default)
Input/Output
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