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HT-CN300H
– 12 –
Figure 12 BLOCK DIAGRAM (3/4)
1
2
3
4
5
6
7
8
9
10
16
15
14
13
12
11
20
19
18
17
OE
D0
D1
D2
D3
D4
D5
D6
D7
GND
VCC
O0
O1
O2
O3
O4
O5
O6
O7
CK
IC702
TVHC574T
LATCH
1
2
3
4
5
6
7
8
9
10
16
15
14
13
12
11
20
19
18
17
OE
D0
D1
D2
D3
D4
D5
D6
D7
GND
VCC
O0
O1
O2
O3
O4
O5
O6
O7
CK
IC701
TVHC574T
LATCH
1
2
3
4
5
6
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A14
A17
VCC
VPP
A16
A15
OE
O6
O5
O4
O3
GND
O2
O1
O0
A0
A1
A2
A3
A4
A5
A6
A7
A12
A13
A8
A9
A11
O7
CE
A10
IC703
MX27L212
EPROM
39
8
9
10
11
14
15
16
17
4
3
44
43
42
41
40
21
22
25
26
27
28
D7
D6
D5
D4
D3
D2
D1
D0
IC706
CS493292
DSP
RD
XMT958
MCLK
SCLK
LRCLK
AUDAT0
AUDAT1
CS
SCDOUT
INTREQ
EXTMEM
SDATAN1
SCLKN1
LRCLKN1
SDATAN2
RESET
SCLKN22
AUDAT2
3
GND
3Y
1A
VCC
1Y
3A
IC707
TC7WU04U
DUAL2-INPUT
NAND GATE
IC704
74HC07AF
BUFFER AMP.
2
37
RX4
SDTI3
SDA/CDTI
XTI/EXTCLK
MCKO
LRCK
BICK
STDO
SDTI1
SDTI2
SCDIN
15
81
82
F_SP_RLY
C_SP_RLY
80
79
S_SP_RLY
W_SP_RLY
29
30
30
X901
8.38 MHz
13
X701
12.288 MHz
SDATAN1 30
VCC
GND
8
4
+B5A
IC710
IX0489AW
SYSTEM
MICROCOMPUTER
FROM
DISPLAY SECTION
+B4A
+5V
+3V3
FLD_SDATA
FLD_SCK
FLD_CS
FLD_RESET
RXIN
DD_LED
STD_LED
DTS_LED
VIR_LED
AAC_LED
DPL_LED
POWER
S_MUTE
ROM
DSP_RESET
DSP_CS
DSP_SCLK
DSP_SCOUT
DSP_SCDIN
SCL
SDA
DSP_UC15
DSP_UC16
DSP_UC17
8
7
9
10
11
12
11
1
35
2
1
23
24
DGND1
DGND3
AGND
DGND2
VD1
VD3
VD2
13
12
13
12
11
10
9
8
1
2
3
4
5
6
36 18 19 20 6
1 6 7
GND
3Y
1A
VCC
IC721
TC7WU04U
DUAL2-INPUT
NAND GATE
1
2
GND
1Y
1I0
VCC
6
5
IC722
74HC153
DIGITAL
SWITCHING
7
1I1
7
14 S0
16
7
14
7
47 45
48
65
39 38 37 36 35
1
2
3
3
VCC
GND
VOUT
IC709
GP1FA550R
DIGITAL IN
CON707
2 3 4
1
20 22 23
25 26 27
24
78 72
Q
Q
Q
+B3A
+B5A
+B4A
Q
+B7A
+B5A
+3V3
16
+B5B
+2V5
+B5
+3V3
+B5
+3V3
+3V3
+11V
+3V3
+5V
SWITCHING
SWITCHING
SPDIF COAX IN
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