Read Sharp CD-C471H (serv.man13) Service Manual online
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CD-C471H
Function
Terminal Name Input/Output
49*
PW
Output
Output terminal of subcodes P, A, R, S, T, U and W.
50*
SFSY
Output
Output terminal of synchronous signal of subcode frame. It drops when subcode stands by.
51
SBCK
Input
Clock input terminal to read subcode. Schmit input (Connected to 0V when not used.)
52*
FSX
Output
Output terminal of synchronous signal of 7.35kHz divided from quartz oscillation.
53
WRQ
Output
Output terminal to stand by output of subcode Q.
54
RWC
Input
Input terminal of read/write. Schmit input.
55
SQOUT
Output
Output terminal of subcode Q.
56
COIN
Input
Command input terminal from microcomputer.
57
CQCK
Input
Clock input terminal to fetch command input, or pick up subcode from SQOUT. Schmit input
58
RES
Input
Reset input terminal of LC78622. When turning on power, set it at "L".
59*
TST11
Output
Output terminal for test. Used in the open state ("L" output as ordinary).
60*
16M
Output
Output terminal of 16.9344Hz.
61
4.2M
Output
Output terminal of 4.2336MHz.
62
TEST5
Input
Input terminal for test Pull-down resistor is integrated. Surely connected to 0V.
63
CS
Input
Chip selection input terminal. Pull-down resistor is integrated.
Connected to 0when not controlled.
Connected to 0when not controlled.
64
TEST1
Input
Input terminal for test Pull-down resistor is integrated. Surely connected to 0V.
Pin No.
Note: The same potential must be supplied to the power terminals (VDD, VVDD, LVDD, RVDD, XVDD).
In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.
DEFI
EFMIN
FSEQ
V/P
PW
SBCK
SBSY
SFSY
CS
WRQ
SQOUT
COIN
RWC
CQCK
HLF
TES
TOFF
JP-
JP+
RES
TGL
CONT1
CONT2
CONT3
CONT4
CONT5
EMPH
EFLG
16M
4.2M
XVss
FSX
XIN
XOUT
XV
DD
RVss
RV
DD
MUTER
RCHO
LCHO
MUTEL
LVss
LV
DD
(NC)
DOUT
C2F
EFMO
VV
DD
VVss
PDO
I SET
FR
PCK
TAI
TSTI1
TEST1
TEST2
TEST3
TEST4
TEST5
V
DD
Vss
CLV+
CLV-
Slice level
control
VCO colck oscillation
clock control
2 K x 8 b i t
R A M
RAM address
generator
Interpolation mute
Bilingual
Digital OUT
Digital
attenuator
X4 oversampling
digital filter
1 b i t D A C
L . P . F
XTAL system timing
generator
General-use port
Servo commander
É C O M
Interface
Subcode division
QCRC
C L V
Digital servo
Sync detection
EFM demodulation
Flag processing of C1/C2
error detection and correction
Figure 49 BLOCK DIAGRAM OF IC
IC2 VHiLC78622K-1:Servo/Signal Control(LC78622K) (1/2)
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