Read Panasonic TX-LR50B6 Service Manual online
TX-LR50B6
30
9 Block Diagram
9.1.
Main Block Diagram
Panel
S5/ S3.3
S3.3
NAND
Flash
1G
XNFCE,XNFW
P
NFCLE,NFALE
XNFWE,XNFR
E
NANDRYBY
NFD[7:0]
P
NFCLE,NFALE
XNFWE,XNFR
E
NANDRYBY
NFD[7:0]
Support
Card
DTV_XRST
CPU BUS
BOOTSWAP
XRST
XRSTSTM
XRST
XRSTSTM
XERWE0
XERWE0
XECS1
ERXW
ES0
ES1
ES2
XERWE0
XECS1
ERXW
ES0
ES1
ES2
ED[
䠓
䠓
:0]
AAR/DATA
CTRL
ED[7:0]
DMD
P-IIC2 (For DMD only)
ADC
DTV Decoder
SIF Decoder
IPR INS
Analog Video
Processor
Video
Format
Processor
VIF Decoder
I2S
SW
SW
AMP
PWM
SPDIF
SW
A-Chip
CLK
GEN
GEN
A-D Chip
Internal BUS
IIC
DMD-IIC0
DMD-IIC1
DMD-IIC1
Trans Port Decoder
CPUBUS
NAND-IF
Peaks
sLD8
STB3.3
STB1.2
STB1.2
IIC
STM-IIC
Serial
STM-Serial0
STM-Serial1
STM-Serial1
25MHz
STM
USB
S5
USB
Power SW
USB*VBUS >
< USB*OC
< USB*OC
S5
S5
USB Memory
86%,)
᧤SRUW᧥
<
㻌 KEY1
POWER KEY
CONTROL PANEL KEY
Cross Stream Switch
D-Chip
IIC
P-IIC0
P-IIC1
P-IIC1
Serial
P-Serial0
P-Serial1
P-UART0
P-UART2
P-Serial1
P-UART0
P-UART2
DMD IIC
DMD_IIC0
DMD_IIC1
DMD_IIC1
EEP
S3.3
EEP
EEPROM_WP
P-IIC
For Peaks
DSP
HDMI
Rx
MUX
x3
/9'67[
PLQL/9'67[
2G - Function
VIErA-CAST Browser
EU MHP
UK BBC iPlayer
Latin GINGA MHP
VIErA-CAST Browser
EU MHP
UK BBC iPlayer
Latin GINGA MHP
''5,)
S1.5
DDR3+(1333)
x16
1G
Tc
o
o
n
Back Light
INVERTER
or
LED Driver
BL_ON >
BL_SOS <
BL_SOS <
S12
Peaks
DCDC
DCDC
䠄VM䠅
S1.1
S1.5
S3.3
STB3.3
STB1.2
STB1.2
STB_XRST
< TV_SOS
AMP/HP MUTE
MONITOROUT MUTE
AMP/HP MUTE
MONITOROUT MUTE
S12/S5
STB5/5VS
Analog
ASIC
ASIC
AN34043A
OVP
SOS
SOS
Safety
Circuit
Circuit
< MON_MUTE
< SP_HP_MUTE
< SP_HP_MUTE
STB3.3V/1.2V_REG
STB5V Reset IC (STM)
S9V_REG
S12V Reset IC (Peaks)
Audio MUTE
OCP/OVP/TV-SOS
HP_MUTE,EXT_MUTE
UHS-I_REG
TV_SOS
PWM
STB5V Reset IC (STM)
S9V_REG
S12V Reset IC (Peaks)
Audio MUTE
OCP/OVP/TV-SOS
HP_MUTE,EXT_MUTE
UHS-I_REG
TV_SOS
PWM
3.3/1.8
UHS-1
UHS-1
REG
3
3
3
3
/
/
1
1
8
8
S9-REG
S9
(SD-Data-VCC)
< (SDVOLC)
DCDC_EN
DTV_XRST >
SW_OFF_DET >
XRST
POWER_DET
PWM >
PWMA
PWM >
<
㻌
KEY3
LVDS
HD : (DATA 4pairs / CLK 1pair) single8bit
FHD: (DATA 4pairs / CLK 1pair) dual8bit
DDR3
AIO
VIO
V-SW
A-SW
LAN
(7+(5
3+<
6',)
SD
㻌 CARD
JTAG
JTAG
DDR3+(1333)
x16
1G
S1.5
AFB
S12
S3
3 3
DC
DC
DT
T
SW
W
Peaks
DCDC
DCDC
SOUND_VCC
PWM
AMP
LV4923V
R1, G1, B1, V1
LIN2, RIN2
Optical OUT
OPT
DDC* > STM, Peaks
HPD* < STM
HDMI_5V_DET* > STM
HDMI_5V_DET* > STM
HDMI1
DDC* > STM, Peaks
HPD* < STM
HDMI_5V_DET* > STM
HDMI_5V_DET* > STM
HDMI2
Rx*
Rx*
IECOUT
Head
Phone
Phone
HP1_L/R
HP_DET
Vout
Lin1,Rin1
Lout,Rout
FB,SLOW,QLINK
Y2,Pb2,Pr2/V2
R3, G3, B3, H,V
HS1BCLKIN
HS1SYNCIN
HS1VALIN
HS1DIN0
HS1DIN1
HS1DIN2
HS1DIN3
HS1DIN4
HS1DIN5
HS1DIN6
HS1DIN7
HS1DIN8
HS1SYNCIN
HS1VALIN
HS1DIN0
HS1DIN1
HS1DIN2
HS1DIN3
HS1DIN4
HS1DIN5
HS1DIN6
HS1DIN7
HS1DIN8
TS-IN
S3.3 / TU1.8
Terrestrial
㻌 or㻌
Terrestrial / Satellite
TUNER
IF_AGC1
1stLow_IF
䚸IFAGC
Terrestrial
DMD_IIC0
Low-IF2
< FE_XRST
䠚
DVB-T2
Demod.
Demod.
DCDC
1.1V
S3.3
Satellite
IF_AGC2
Low-IF1
2ndLow_IF,IFAGC
CXD2837
< FE_XRST
䠚
DMD_IIC1 (IIC2)
S3.3
Only㻌 DVB-T2㻌 models
DMD_IIC1 (IIC2)
< FE_SAT_RST
䠚
SAT2.5 / SAT1.2
CI
PCOE
PCWE
PCIORD
PCIOWR
PCRESET
PCCE1
PCWE
PCIORD
PCIOWR
PCRESET
PCCE1
CI-IF
PCWAIT
PCCD1
PCCD2
PCREADY
PCCD1
PCCD2
PCREADY
CI-IF
(5V Tolerant)
(5V Tolerant)
ED[7:0]
Data Buffer
PCDOE
ERXW
ERXW
TS-IN
TS-OUT
(5V Tole)
(5V Tole)
CI
Power
Circuit
Circuit
CI_POWER_ON
>
<
CI_OCP
ALRCKO
ASDOUT0
ABCKO
ASMCK
ASDOUT0
ABCKO
ASMCK
ARCOUT
No use 24/19XM6
LNB
Only㻌 SAT㻌 models
R3, G3, B3, H,V
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