Read Panasonic KX-UT670RU Service Manual online
14
KX-UT670RU
4.6.
Reset Circuit
The RESET signal is output from the port of POR_RST_B according to the voltage value(3.3V) supplied to IC1 and the voltage
value that IC generates.
This RESET signal flows in order of pin2 of IC402,pin4 of IC402, and R408.
Low level period of RESET signal needs more than 100ms.
value that IC generates.
This RESET signal flows in order of pin2 of IC402,pin4 of IC402, and R408.
Low level period of RESET signal needs more than 100ms.
The reason to have taken out this RESET signal outside is for use of development.
4.7.
Ethernet Circuit
IC1(CPU) has PHY function for the interface of ETHERNET and has ETHERNET function 10Base-T,
100Base-TX and 1000Base-T.
It is composed of a simple circuit as shown in the above figure.
100Base-TX and 1000Base-T.
It is composed of a simple circuit as shown in the above figure.
LAN port, PC port, and IC1 are insulated mutually electrically.
The power supply for PoE is obtained from JK1 on LAN port side.
As for the voltage generated from PoE, 12V is output by the operation explained by 4-2.
The power supply for PoE is obtained from JK1 on LAN port side.
As for the voltage generated from PoE, 12V is output by the operation explained by 4-2.
IC402
1
*G
2
A
4
Y
5
VCC
3
GND
R418 10k
R419
1k
DG
3.3V
R408
0
R417
2.2k
R482
NC
C417
1u
C459
1u 6.3
E17
BBL_VDD
BBL_VDD
E18
BBL_AVSS
BBL_AVSS
AE3
RST_B
RST_B
AC2
POR_RST_B
POR_RST_B
R1
XTALP
XTALP
T1
XTALN
XTALN
D21
NC3
NC3
T5
NC4
NC4
AA15
NC5
NC5
AE4
NC6
NC6
EPHY0_TX0_P
EPHY0_TD0_N
EPHY0_TD1_P
EPHY0_TD1_N
EPHY0_TD2_P
EPHY0_TD2_N
EPHY0_TX3_P
EPHY0_TX3_N
EPHY1_TX3_P
EPHY1_TX3_N
EPHY1_TX2_P
EPHY1_TX2_N
EPHY1_TX1_P
EPHY1_TX1_N
EPHY1_TX0_P
EPHY1_TX0_N
PoE_Pluse
JK2
1
2
3
4
5
6
7
8
9
R1
75
R2
75
R3
75
R4
75
G
C2
0.1u 25
C5
0.1u 25
C6
0.1u
25
C7
0.1u
25
C8
0.1u
25
C9
0.1u
25
R5
75
R6
75
R7
75
R8 75
C10 0.1u 250
C11
0.1u 250
C12 0.1u 250
C13 0.1u 250
G
D1
4
1
3
2
D2
4
1
3
2
JK1
1
2
3
4
5
6
7
8
2
3
4
5
6
7
8
9
DG
DG
DG
C3
0.1u 25
C4
0.1u 25
R43
1.24k
C144
0.1u
250
C145
0.1u
250
C146
0.1u
250
C147
0.1u
250
L25
L24
L23
L22
E_EXTVREF
TVCOI
DG
DG
DG
DG
DG
DG
DG
DG
D22
D21
D24
D23
D26
D25
D28
D27
D29
D30
D31
D32
D33
D34
D35
D36
SGMII_SEL
SGMII0_RXDN
SGMII0_RXDP
SGMII0_TXDP
SGMII0_TXDN
SGMII0_TXDN
SGMII1_RXDP
SGMII1_RXDN
SGMII1_RXDN
SGMII1_TXDP
SGMII1_TXDN
SGMII1_TXDN
SGMII_CLKP
AD21
EPHY0_TD0P
SGMII_CLKN
NC7
NC8
NC8
AE21
EPHY0_TD0N
AD20
EPHY0_TD1P
AE20
EPHY0_TD1N
AD19
EPHY0_TD2P
AE19
EPHY0_TD2N
AD18
EPHY0_TD3P
AE18
EPHY0_TD3N
AD22
EPHY1_TD0P
AE22
EPHY1_TD0N
AD23
EPHY1_TD1P
AE23
EPHY1_TD1N
AD24
EPHY1_TD2P
AE24
EPHY1_TD2N
AC25
EPHY1_TD3P
AD25
EPHY1_TD3N
AC19
EPHY_RDAC
AC20
EPHY_EXTVREF
AB20
EPHY_TVCOI
T1
4
20
5
24
21
19
22
3
2
1
6
23
17
16
18
13
15
14
12
11
10
9
8
7
T2
4
20
5
24
21
19
22
3
2
1
6
23
17
16
18
13
15
14
12
11
10
9
8
7
1
C14
33p
2000
C1
33p
2000
C240
NC
C241
NC
LAN
PC
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