Read Panasonic PT-RQ32K Service Manual online
DIA-7
SCHEMATIC DIAGRAMS
< RQ32K >
1. 6. Signal Block Diagram (DG-PCB/DF-PCB)
FPGA3
LVDS 22pair
RGB/H/V/ACT/CLK
LVDS 24pair
RGB/H/V/ACT/CLK
LVDS 12pair
H/V/CLK
X4201
20MHz
132MHz
132MHz
132MHz
IC4201
IC4502/IC4503
DDR3 SDRAM
IC4504
DDR3 SDRAM
IC4702/IC4703
DDR3 SDRAM
IC4704
DDR3 SDRAM
CPLD2-->FPGA3 CONFIG
FPGA3-->WARP
CPLD2-->FPGA3 LVDS I/F
CPLD1-->CPLD2 IIC
CPLD2-->CPLD3 IIC
CPLD2-->CPLD3 LVDS I/F
CPLD2-->CPLD3 IIC
CPLD2-->CPLD3 LVDS I/F
CPLD2-->CPLD3 IIC
CPLD2-->CPLD3 LVDS I/F
CPLD1-->CPLD2 LVDS I/F
To A-P.C.B
(A2)
To A-P.C.B
(A3)
PICTURE CONTROL
・
APL DET
・
SIGNAL AI
・
HV ENHANCER
・
SYSTEM DLV
・
EDGE BLENDING
・
UNIFORMITY
・
COLOR MATCHING
・
CURSOR DISPLAY
・
WAVEFORM MONITOR
DG-P.C.B
X4202
X4203
X4204
CPLD2
・
FPGA3, WARP P-on control
・
FPGA3 control
IC4401
FLASH ROM
IC4402
IC4205, IC4206, IC4207
IC4208, IC4209
DDR3 SDRAM
DG3
DG2
DG1
WARP
IC4501
WARP
IC4701
LVDS 12pair
AURORA 4pair
PWRGOOD/BUSY/BOOT_HOLD
INT/PROTECT
IIC_POWER/IIC_STB
CLK 1pair, SYNC3
RST, etc
4
PWRGOOD/BUSY/BOOT_HOLD
INT/PROTECT
IIC_POWER/IIC_STB
AURORA 4pair
CLK 1pair, SYNC3
RST, etc
4
LVDS 12pair
LVDS 12pair
X5004
20MHz
132MHz
132MHz
132MHz
IC5502/IC5503
DDR3 SDRAM
IC5602/IC5603
DDR3 SDRAM
CPLD3-->FPGA4 CONFIG
FPGA4-->FRC
CLK to FRC#0/#1/#2/#3
H/V
CLK
EXBUS
CPLD3-->FPGA4 LVDS I/F
CPLD3-->CPLD4 IIC
CPLD3-->CPLD4 LVDS I/F
To PB-P.C.B
(PB4)
DF-P.C.B
X5001
X5002
X5003
CPLD3
・
FPGA4, FRC P-on control
・
FPGA4 control
IC5201
FLASH ROM
IC5202
IC5011, IC5021,
IC5031, IC5041
DDR3 SDRAM
DF1
DF3
To DP-P.C.B
(DP1)
DF2
FRC#1
IC5501
FRC#0
IC5401
FRC#2
IC5601
FRC#2
IC5701
LVDS 12pair
LVDS 12pair
IC5402/IC5403
DDR3 SDRAM
IC5702/IC5703
DDR3 SDRAM
AURORA 4pair
PWRGOOD/BUSY/BOOT_HOLD
INT/PROTECT
IIC_POWER/IIC_STB
CLK 1pair, SYNC3
RST, etc
4
AURORA 4pair
CLK 1pair, SYNC3
RST, etc
4
FPGA4
IC5001
IMAGE CONTROL
・
4K --> 5K CONVERSION
LVDS 12pair
+16V_DG1
+16V_DG2
+16V_DP1
+16V_DP2
+16V_DF1
+16V_DF2
LVDS 12pair
LVDS 12pair
LVDS 12pair
CLK
CLK
CLK
1
3
5
7
9
11
DF2
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