KX-PX1CX - Panasonic Copying Equipment Service Manual (repair manual). Page 20

20

186

B9 PP[20]/

DACK#[2]/
DREQ#[6] 

Dmac ch.2 
ACKnowledge/
Dmac ch.6 transfer 
REQuest/GPIO 20

Common terminal for the trans-
mission acknowledge on DMAC 
ch.2, the transmission request on 
DMAC ch.6, and the general-pur-
pose input and output port 
(GPIO)

MOTSTOP

Disable Motors_control of 
the mechanical CPU 
Forced stop of the motor

out

271

C9 PP[21]/

DACK#[3]/
DREQ#[7] 

Dmac ch.3 
ACKnowledge/
Dmac ch.7 transfer 
REQuest/GPIO 21

The transfer acknowledge on 
DMAC ch.3, the transmission 
request on DMAC ch.7, and the 
general-purpose input and out-
put port (GPIO)

FLMD#

Set mechanical CPU into 
programing mode 
For writing the ROM 
inside the mechanical 
CPU

out

57

Y26 

PRST# 

Power-on ReSeT

Reset signal (16 CLKIN clock 
cycles)

FR_RST# 
CN13-11 
78K_P62

Reset input 

in

239

Y24 RAM-

BOOT#

RAM BOOT

A software reset is caused by 
applying the 'L' level. At the time 
of power on reset, reflection to 
the SA bit of HSR0 is made. 
In the case of 'L' level: 
0x00000000 
In the case of 'H' level: 
0xFF000000

H' 33k 
Pull_UP

Not used

in

263

C17 

RD# 

ReaD

An assertion is made after the 
second cycle of the read cycle.

CPRD# 
IC5FROM_*O
E 

Read signal 
ROM readout

out

340

D17 

RDY# 

ReaDY

The bus cycle completion notifi-
cation is input. 
When RSTOUT# is asserted, the 
value of RDY# is reflected to 
LCR0.RC

33k Pull_UP

Not used

in

321

U23 

RSTOUT#  ReSeT OUTput

RESET output

33k Pull_UP

Not used

out

297

AC5 

SCL[0] 

I2C clock: channel 
[0]

I2C clock: channel [0]

SCLO 
78K_P60 
SCL0

I2C clock signal to the 
mechanical CPU 

out

216

AD5 

SCL[1] 

I2C clock: channel 
[1]

I2C clock: channel [1]

Set N.C. out-
put to Low 
(Check is 
required)

Not used

out

215

AD4 

SDA[0] 

I2C data: Channel 
[0]

I2C data: Channel [0]

SDA0 
78K_P61 
SDA0

I2C data signal to 
mechanical CPU 

I/O

126

AE4 

SDA[1] 

I2C data: Channel 
[1]

I2C data: Channel [1]

Set N.C. out-
put to Low 
(Check is 
required)

Not used

out

351

D6 

SDCD 

SD insertion and 
extraction signal

SD insertion and extraction signal High 3.3v

Not used

in

189

B6 

SDCKI 

Clock input for SD

Clock input for SD

High 33k 
Pull_UP

Not used

in

272

C8 

SDCLK 

Transfer clock out-
put for SD and mem-
ory stick

Transfer clock output for SD and 
memory stick

N.C.

Not used

out

95

A7 

SDCMD 

Input and output of 
the SD command

Bus state of the serial interface

N.C. 33k 
Pull_UP

Not used

I/O

188

B7 

SDDAT[0] Data signal for SD

Data signal for SD

N.C. 33k 
Pull_UP

Not used

I/O

273

C7 

SDDAT[1]  Data signal for SD

Data signal for SD

N.C. 33k 
Pull_UP

Not used

I/O

350

D7 

SDDAT[2] Data signal for SD

Data signal for SD

N.C. 33k 
Pull_UP

Not used

I/O

419

E7 

SDDAT[3]  Data signal for SD

Data signal for SD

N.C. 33k 
Pull_UP

Not used

I/O

294

AA4 

SDI/DR

Audio data input

Input the audio serial data 

Low GND

Not used

in

420

E6 SDMSSE-

LECT 

SD/memory stick 
selection signal 
input

H:SD L:MS

High 33k 
Pull_UP

Not used

in

213

AC3 

SDO/DX 

Audio data output

Audio serial data output is pro-
duced

N.C.

Not used

out

pin 

No.

pin

assign

ment

Name of 
the CPU 

terminal

VDE

VDD

Signal name 

of the CPU 

(IC3) on the 

main board

Purpose of the signal

I/O