DP-8020E, 8020P*, 8016P (serv.man2) - Panasonic Copying Equipment Service Manual (repair manual). Page 7

7

DEC 2006

Ver. 1.0

DP-8020E/8020P*/8016P

1. System CPU

The System CPU (PPC405PM) is a 32-bit RISC (Reduced Instruction Set Computer) type of CPU and
EBC Control (ROM/SRAM), PC100 SDRAM Control, PCI Control, DMA Control, Serial Communication 
Port, Timer, Interrupt Control, Ethernet MAC and IIC Control are integrated into 1 chip. 
The EBC is connected to the Power-on Boot space. The 405 processor will begin with an initial fetch to 
address 0xFFFFFFFC. The EBC is setup to respond to this Boot address and the request is directed to 
bank 0. This bank must have a ROM attached with the Boot code to begin the processor execution.

• EBC Control

A 7-port peripheral bus control, used to transfer data between the following devices.
Boot ROM (IC12)
Main Program F-ROM (IC2)
System Backup F-ROM (IC3)
API (IC11)
Option Card Slots (CN62)
Option FAX Board

• SDRAM Control

Generates High Speed SDRAM Control Signal and Refresh Control when the power is ON.

• PCI Control

A 6-ch PCI control bus, used to transfer data between the following devices.
Imaging ASIC (ISIS2)

• Serial Communication Port

A 3-ch Serial Communication Port, used to interface the following devices.
CPU: Panel Unit (Panel CPU)
CPU: Sub CPU for Scanning and Printing (M16C/80)
CSS Debug Port for PC

• Timer Control

Used to program the standard timer.

• Interrupt Control

Controls receipt & transfer to CPU the interrupt from ISIS2, Modem, LSI, Option, etc.

• I/O Port (DZAC000332)

Used to control lines and reset control around LSI, etc.

• Ethernet MAC

Supports Auto-sensing 10Base-T/100Base-TX, Full / Half Duplex modes.

• IIC Control

A 1-ch IIC Port, used to interface for SPC Program Download.