Read Panasonic TH-50PF10RK Service Manual Simplified online
TH-50PF10RK
6
5.2.
HDMI-Board (2 of 2) Block Diagram
SLOT_SRQ
SLOT_SCL
SLOT_SDA
SLOT_SCL
SLOT_SDA
SLOT_SRQ
SLOT_SDA
SLOT_SCL
CMD_SDA
CMD_SCL
GENX_NBOOT
PLUG_DET
HD/FHD_DET
EX_RESERVE1
CH_SEL
EX_RESERVE2
EX_RESERVE3
SLOT_SDA
SLOT_SCL
HPD1
HPD2
EDID_WP
CH_SEL
EX_RESERVE1
EX_RESERVE2
EX_RESERVE3
TV/LOAD_CMD_SCL
TV/LOAD_CMD_SDA
HDMI_L
HDMI_R
HD/FHD_DET
A7
VCCA_PLL1,2
A15
A9
A13
A10
A4
B15
A2
B11
B8
LVDS_TX9+
B9
B5
A3
B6
B3
VCC02
B14
B12
B2
LVDS_TX9-
GENX_LYDS_PWD
SYG_TYPE0
IC3314
VDD
RESET
IC3312
VOUT
1
+3.3VREG
CONFIG ROM(FPGA)
TO
2
8
VCC
DATAO
IC3341
+3.3VREG
nCSO
FPGA
DATA
5
NCS
1
A12
DCLK
DCLK
A5
ASDI
ASDO
Y0,Y1
3
6
UV0,UV1
A14
H1
A8
LX
D2
18
S1
OUT-2
D2
G1
VO
16
24
FB
S2
23
+3.3VREG
-INC
D1
OUT-1
D1
19
Q3237
13
G2
VIN
VDD
21
17
VCC
5
15V->3.3V
IC3339
DC-DC CONVERTER
LVDS18p
LVDS18n
LVDS23p
LVDS23n
LVDS27p
LVDS27n
LVDS31p
LVDS31n
LVDS34n
LVDS34p
LVDS19p
LVDS35n
LVDS28p
LVDS19n
LVDS37n
LVDS33n
LVDS33p
LVDS35p
LVDS28n
LVDS37p
LVDS26n
LVDS26p
FOR
2
5
H2
EPCS_DATA
FPGA_NCE
9
RESET
10
1
7
4
GND
EPCS_DCLK
+3.3V
6
EPCS_ASD
FACTORY
USE
USE
EPCS_NCS
8
3
CONFIG DONE
B19
A19
A21
B21
A22
B23
A23
B24
B25
A28
A26
B28
B37
B38
B39
DS12
5
SLOT_SDA
2
1
H3
7
4
USE
SRQ
+5V
TVLOAD_CMD_SCL
6
GENX_BOOT
GND
3
8
FOR
H_WP
SLOT_SCL
9
FACTORY
TVLOAD_CMD_SDA
PLUG DET
+15V
+15V
PLUG DET
HDMI_R
HDMI_L
SLOT_SCL
SLOT_SDA
HD/FHD DET
SLOT_SRQ
+5V STB
+9V
+9V
+5V
+5V
+5V
5V
+9V
9V
5VSTB
+5VSTB
LVDS_TX8-
LVDS_TX8+
LVDS_TX6+
LVDS_TX6-
LVDS_TX7-
LVDS_TX7+
LVDS_TX5+
LVDS_TX5-
LVDS_TX3+
LVDS_TX2+
LVDS_TX0+
LVDS_TX3-
LVDS_TX0-
LVDS_TX1-
LVDS_TX4-
LVDS_TX4+
LVDS_TX1+
LVDS_TX2-
LVDS_TXC+
LVDS_TXC-
CONFIG_DONE
nCE
15V
3.3V
TP3334
IC3344
VDD
6
VOUT
1
+2.5V
+3.3VREG
+2.5V
+1.2V
4
+1.2V
OUT
IC3342
2
VCC
VCCI01,03,04
SYG_TYPE3
RESERVE1
RESERVE6
FPGA_RST
N_FHD
Y2-Y9
UV2-UV9
DP_CLK
VS
HS
DE
HDMI_5V_DET1
HDMI_5V_DET2
EDID_WP
O_CLK
S2
S1
S0
CLK4
CLK1
S3
1
2
3
4
6
8
7
IC3343
CPG
S2
FIN
S1
S0
FOUT
S3
VDD
nCONFIG
+3.3VREG
CONFIG
IC3319
ROM
VCC
8
5
SDA
6
7
WP
SCL
+5VSTB
Y2-Y9
UV2-UV9
Y0,Y1,UV0,UV1
DCK
VSYNC
HSYNC
DE
TP3346
CLK
VS
TP3343
TP3345
HS
TP3344
DE
+5V
IC3338
1
5
AVR+5V
+15V
EXPAND I/O
IC3321
4
P0
P1
5
6
P2
P3
16
+5VSTB
VCC
16
SCL
SDA 15
7
4
5
BUFFER
VCC
IN_A
OUT_Y
2
IC3329
+3.3VREG
+3.3VREG
OUT_Y
4
IC3330
VCC
BUFFER
5
2
IN_A
IC3310
MAIN MICOM
127
HDMI_DAC_PDWN
83
OSCXO
OSCXI
84
SDA0
39
40
SCL0
HDMI_RST
45
HDMI_INT
68
HPD2
57
56
HPD1
+5V
D3334
+5V_A
D3333
D3332
+5V_B
ADIN1
112
113
114
115
64
63
ADIN2
ADIN4
ADIN3
SCL1
SDA1
HDMI_A_MUTE
126
5
SIGTYPE3
8
SIGTYPE0
RESERVE1
124
125
12
15
RESERVE6
GNX_LVDS_PWD 33
FPGA_RST
111
N_FHD 46
53
HDMI_5V_DET1
52
HDMI_5V_DET2
NBOOT 92
NRST 93
IVDO
+3.3VREG
X3302
10MHz
10MHz
Q3312
A-MUTE
Q3313
INV.
Q3328
AMP
Q3314
AUDIO
MUTE
AUDIO
MUTE
Q3315
AUDIO
MUTE
AUDIO
MUTE
2
3
5
6
1
8
7
+9V
+9V
AUDIO AMP_R
IC3322
1
7
3
2
5
8
6
+9V
AMP
Q3329
AUDIO AMP_L
IC3323
GENX_HR_EEP_SDA
GENX_HR_EEP_SCL
HDMI_5V_DET2
HDMI_5V_DET1
GENX_NBOOT
FHD
HD
(CONTROL BUS)
1
2
3
5
6
7
4
10
9
8
TH-50PF10RK
HDMI-Board (2 of 2) Block Diagram
HDMI-Board (2 of 2) Block Diagram
TH-50PF10RK
HDMI-Board (2 of 2) Block Diagram
HDMI-Board (2 of 2) Block Diagram
MICOM
HDMI
DIGITAL SIGNAL PROCESSOR
HDMI INTERFACE
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