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15.47. D-Board (2 of 2) Block Diagram
CPH1
CSOU
CPH2
CLK
CERS(CBK)
P3V_SCL2
P3V_SCL02
P3V_SD
A02
CEL
OCIA(CL)
CQR_(CPL)
SIUB/LA
T
SCSU
CSL
CML
P3V_SD
A2
OCK
PCK
CLKM
PRCK
SID
A
DRVRST
OC2(CEL2)
SIU
A
DR
V_RST0
OC1B(CL2)
CMH
SIDB(SID2)
CSH
SOS8_SS
SOS6_SC1
SOS7_SC2
ODEU1
LEU1
PCU1
CLR
U1
CLKU7(-)
CLKU6(+)
CLKU5(-)
CLKU4(+)
CLKU2(+)
P+3.3V
P+1.2V
P+2.5V
D9304
D9305
D9303
DET
2
60
33
D13C
SIUB/LA
T
(D22A-D31C)
67
35
VCC
8
(U10A-U15C)
68
59
60
DATA 30Bit
DDR-DRAM R
36
39
31
SCAN CONTROL
LED5
Q9303
13
5
DET
128Mbit
DATA PROCESS
2
C40
CLKU0(+)
14
3
75MHz
7
SUB FIELD
P+5V
DATA CONTROL 8bit
75MHz
36.6MHz
CLKD7(-)
41
1
CLKU6(+)
1
60
C41
61
*CONTOUR CORRE.
*S/P CONV.
3.3V->5V
DATA 18Bit
DATA PROCESS
SUSTAIN CONTROL
+5V
Q9301
32
MPEG
41
CLKD6(+)
DATA 18Bit
40
68
CLKU0(+)
P+5V
CLKU1(-)
9
11
42
37
PCD5
CLKU3(-)
PCK
USL
2
DDR-IO
CLKU7(-)
24
PCK
DET
CLKD3(-)
58
UMH
11
OCK
RESET
58
CLRD5
CLKD2(+)
6
+5V
UML
CLKD5(-)
CLRD6
128Mbit
DDR-DRAM L
28
ODED6
64
D36
64
CLKD4(+)
67
55
SC20
PCK
(D0A-D9C)
SIU
A
3.3V->5V
USH
VDD33
CEL
IIC
LED6
ODED5
4
35
CLK
19
CPH2
SCAN CONTROL
DATA 16bit
DATA 16bit
11
45
DATA 30Bit
+5V
34
CLKU5(-)
CONTROL
PROCESSOR
3.3V->5V
D10A
MPEG
8
CML
SOS8_SS
CLKD7(-)
NOISE REDUCTION
PCD6
2
29
PLASMA AI PROCESSOR
+5V
*DATA DRIVER
D
VDD25
P+2.5V
52
5
FORMAT CONVERTER,
P+5V
CONT
NUEL
LEVEL SHIFT
38
15
D22A
PROCESSOR
CLKD5(-)
66
(D16A-D21C)
LEVEL SHIFT
CLOCK
11
64
DET
PCD6
LED5
CLK OUT
*CONTOUR CORRE.
DATA 30Bit
63
56
LEVEL SHIFT
15
30
17
DATA 30Bit
DATA 18Bit
*S/P CONV.
OC2(CEL2)
28
*SF TABLE CONV.
FLASH
CLRD6
VCC
HD,VD
10
SUB FIELD
5
10
43
OCK
XRST2
*DATA DRIVER
66
G 10bit
OC1A(CL)
34
3
26
CLRD5
+5V DET
CLKU2(+)
38
VCC
14
D20
DATA
(U16A-U21C)
P+5V
I/F
54
CLKD4(+)
IIC
FLASH
P+5V
DATA
VCC
56
CLKD6(+)
13
67
37
CLOCK
17
D34
+5V DET
59
SID
A
BUS SWITCH
61
CERS(CBK)
36
(U0A-U9C)
DATA 4bit
58
1
OCK
ADR
8
9
16
7
P+5V
LED6
27
CLKD3(-)
ODED5
35
CSL
OCK
CSOU
VCC
DATA
DET
PCK
XRST
39
DATA 18Bit
(U22A-U31C)
59
C30
18
(D10A-D15C)
DDR-IO
UEH
DATA 6bit
36.6MHz
+5V
I/F
CLK OUT
*SF TABLE CONV.
D25C
5
Q9305
CLKU3(-)
CQR(CPL)
9
CONT
12
CONT
Q9302
34
ODED6
62
RESET
CPH1
10
VDDQ/VDD
RESET
P+5V
D35
VDD12
PCD5
33
31
10
SCSU
+5V DET
13
ADR
CLKU4(+)
84MHz
75MHz
VDD
36.6MHz
20MHz
X9200
CPG
CLKD1(-)
CLKD0(+)
CLKD3(-)
CLKD2(+)
CLKD6(+)
CLKD4(+)
CLKD5(-)
CLKD7(-)
ADDRESS
R 10bit
B 10bit
B 10bit
R 10bit
G 10bit
HD,VD
VDD12
VDD33
VDD25
BUS SWITCH
VCC
Q9300
DET
Q9304
+5V
Q9306
INV.
P+3.3V
P+1.2V
P+2.5V
21bit
G
B
10bit
10bit
10bit
R
9bit
P+3.3V
P+2.5V
P+1.2V
16bit
DATA
21bit
ADDRESS
16bit
DATA
16bit
DATA
NOISE REDUCTION
X1
X2
JTAG
DATA CONTROL
8bit
8bit
24
CMH
CSH
25
DR
V_RST0
SIDB(SID2)
OC1B(CL2)
26
22
27
NUEL
USL
USH
UMH
UEH
UML
32
CLKD0(+)
30
CLKD1(-)
CLKD3(-)
CLKD2(+)
CLKD3(-)
CLKD0(+)
CLKD1(-)
P+15V
6
21
30
31
SOS7_SC2
SOS6_SC1
P+15V
P+15V
D31C
D22A
D15C
D15A
D21C
D16A
D10A
D15C
JTAG
64
2
3
30
36
CLKU5(-)
35
5
38
31
13
P+5V
P+5V
U21C
67
68
U17A
1
66
56
CLKU2(+)
P+5V
34
39
+5V DET
33
CLKU4(+)
D32
U16A
28
26
43
U16C
41
67
U15C
24
2
U10A
45
C11
U16A
U21C
U10A
U15C
41
17
28
63
U22A
U27C
52
31
38
6
U28A
U31C
U22A
U31C
32
30
39
37
CLKU7(-)
CLKU6(+)
59
11
ODEU1
9
58
60
PCU1
LEU1
CLR
U1
10
8
61
68
1
3
+5V DET
P+5V
67
64
2
5
66
P+5V
P+5V
D9300
D9301
58
CLRU3
11
CLRU2
PCU3
10
PCU2
59
LEU3
8
ODEU3
9
LEU2
61
ODEU2
60
D31
C10
68
1
P+5V
2
3
P+5V
67
66
P+5V
D33
C20
64
+5V DET
D9302
5
36
33
35
37
39
34
32
30
CLKU1(-)
CLKU2(+)
CLKU3(-)
CLKU0(+)
CLKU2(+)
CLKU1(-)
U0A-U9C
52
31
38
U6A-U9C
17
63
28
6
41
U0A-U5C
67
66
P+5V
P+5V
68
P+5V
2
1
3
21
48
D0A-D1C
27
42
38
40
D3A-D3C
31
29
43
D2A-D2C
26
41
28
D4A-D9C
2
45
24
67
D0A-D9C
IC9304
IC9402
IC9504
IC9807
IC9802
IC9803
IC9803
IC9401
IC9400
IC9300
IC9301
IC9603
IC9200
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
PD1M+(MN84524) Right
PD1M+(MN84524) Left
16Mbit FlashROM
(PDROM)
D26A
D31C
D14C
D14A
D21C
D16A
TH-42PY700F/P, PZ700B/E
D-Board (2 of 2) Block Diagram
D-Board (2 of 2) Block Diagram
TH-42PY700F/P, PZ700B/E
D-Board (2 of 2) Block Diagram
D-Board (2 of 2) Block Diagram
TH-42PZ700B / TH-42PZ700E / TH-42PY700F / TH-42PY700P
117
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