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6.1. BLOCK DISCRIPTION
The BUS-M card consists of the interface with the EMPR, the BMCTL (FPGA) comprising a control circuit within the card, the
CTSW (system TSW) exchanging the PCM highway interface of the basic shelf backboard and the PCM highways of the expansion
shelves, the CircLink (communication controller) realizing the control message communication between the basic shelf and expsion
shelves, the connectors connecting the shelf-to-shelf communication cables, and the differential receiver (LVDS standard)
comprising the differential communication channels.
BMCTL Block
CTSW (system TSW) exchanging the PCM highway interface of the basic shelf backboard and the PCM highways of the expansion
shelves, the CircLink (communication controller) realizing the control message communication between the basic shelf and expsion
shelves, the connectors connecting the shelf-to-shelf communication cables, and the differential receiver (LVDS standard)
comprising the differential communication channels.
BMCTL Block
The BMCTL has a glue logic function to connect the expansion bus of the EMPR card and the internal control bus of the BUS-
M card and a function to terminate and relay the control signals connected to the control register in the BUS-M card and the
expansion shelves.
M card and a function to terminate and relay the control signals connected to the control register in the BUS-M card and the
expansion shelves.
The main functions of the BMCTL are as follows.
1. Termination of the triggers such as CircLink interruption (nINTRRCL1, nINTRCL2, nINTRCL3), cable insert detection
interruption (SSSTAT1, SSSTAT2, SSSTAT3) and line out of sync detection interruption (nLOS1, nLOS2, nLOS3) within the
BUS-M card, and generation of the BUS-M interruption signal (BM_nIRQ) for the EMPR card.
BUS-M card, and generation of the BUS-M interruption signal (BM_nIRQ) for the EMPR card.
2. Generation of reset signal (nMRESET1, nMRESET2,nMRESET3) according to each expansion shelf.
3. Selection of line synchronizing signal (S1_NETREF,S2_NETREF, S3_NETREF) input from expansion shelf and drive of line
3. Selection of line synchronizing signal (S1_NETREF,S2_NETREF, S3_NETREF) input from expansion shelf and drive of line
synchronizing signal line (CT_NETTREF) on basic shelf backboard.
4. Control of maintenance function signal (nCMIBYP3, nDIAG1, nCMIBYP1, nDIAG2, nCMIBYP2, and nDIAG3) control to
CircLink # 1(IC301), # 2, and # 3.
5. Control of output pin enable signal (ODEZL) of CT-BUS switch (IC101).
6. Control of status LED control signal (LED_RED,LED_GR) and link LED control signal (ES1S_LED, ES2S_LED, and
6. Control of status LED control signal (LED_RED,LED_GR) and link LED control signal (ES1S_LED, ES2S_LED, and
ES3S_LED).
7. Register display of extended shelf status display signal (BSOP1,BSOP2,BSOP3).
8. Generation of address decode to CircLink # 1 (IC301), #2, and #3 and chipselect (nCSCL1, nCSCL2, nCSCL3).
9. Generation of address decode to CT-BUS switch (IC101) and chipselect (nCSZL).
CT-BUS switch
8. Generation of address decode to CircLink # 1 (IC301), #2, and #3 and chipselect (nCSCL1, nCSCL2, nCSCL3).
9. Generation of address decode to CT-BUS switch (IC101) and chipselect (nCSZL).
CT-BUS switch
The CTSW has the following functions; 1) to exchange 1536ch of PCM highways in total which consists of 384ch of the
PCM highways on the basic shelf backboard and 1152ch to be connected to three expansion shelves (384ch for each shelf),
2) to generate the PCM highway clock and frame synchronization signal which are distributed among the expansion shelves.
PCM highways on the basic shelf backboard and 1152ch to be connected to three expansion shelves (384ch for each shelf),
2) to generate the PCM highway clock and frame synchronization signal which are distributed among the expansion shelves.
Communication Controller block
The CircLink is a communication controller to realize control message communication between the basic shelf and
expansion shelves. The CircLink chips on expansion shelves and the CircLink chips on the BUS-M card are connected one-
on-one basis. But the CircLink chip initially mounted on the BUS-M card only corresponds to the extended port #1, so the
CircLink chips corresponding to the extended ports #2 and #3 should be added by mounting BUS-ME cards (KX-TDA6111).
expansion shelves. The CircLink chips on expansion shelves and the CircLink chips on the BUS-M card are connected one-
on-one basis. But the CircLink chip initially mounted on the BUS-M card only corresponds to the extended port #1, so the
CircLink chips corresponding to the extended ports #2 and #3 should be added by mounting BUS-ME cards (KX-TDA6111).
Shelf Interface block
The shelves are connected with 20 pairs of twisted pair cables. Three ports of 40 pin half pitch connectors for cable
connections and an LVDS interface ship as a driver receiver of board-to-board signal are mounted on the board.
But the LVDS device initially mounted on the BUS-M card only corresponds to the extended port #1, so the LVDS devices
corresponding to the extended ports #2 and #3 should be added by mounting BUS-ME cards (KX-TDA6111).
connections and an LVDS interface ship as a driver receiver of board-to-board signal are mounted on the board.
But the LVDS device initially mounted on the BUS-M card only corresponds to the extended port #1, so the LVDS devices
corresponding to the extended ports #2 and #3 should be added by mounting BUS-ME cards (KX-TDA6111).
Power block
The BUS-M card uses three types of power supplies; +3.3 V, +2.5 V and +1.2 V. Since a power supply of +15 V is supplied
from the backboard, the power block consists of three types of devices; a DC/DC converter converting +15 V into +3.3 V and
series regulators converting +3.3 V into +2.5 V and +3.3 V into +1.2 V.
from the backboard, the power block consists of three types of devices; a DC/DC converter converting +15 V into +3.3 V and
series regulators converting +3.3 V into +2.5 V and +3.3 V into +1.2 V.
Others
- Mount two 120 pin board-to-board connectors on the board for mounting 2 ports of the BUS-ME cards.
- Since the BMCTL is implemented by SRAM-type FPGA (IG614), it is necessary to read the configuration data during start-
up. The configuration data is stored in a serial PROM (IC210). The reading of the configuration data occurs when power is
on and the EC_nRST signal is asserted. Since the status of the internal register is random just after the completion of
configuration, it requires logical reset by the EC_nRST.
- Since the BMCTL is implemented by SRAM-type FPGA (IG614), it is necessary to read the configuration data during start-
up. The configuration data is stored in a serial PROM (IC210). The reading of the configuration data occurs when power is
on and the EC_nRST signal is asserted. Since the status of the internal register is random just after the completion of
configuration, it requires logical reset by the EC_nRST.
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KX-TDA6110XJ / KX-TDA6110X
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