Read Panasonic KX-TDA3168XJ / KX-TDA3168X (serv.man3) Service Manual Supplement online
Signal Name
I/O
Pin No.
DESCRIPTION
NWR
in
32
Write enable signal (Low Active) (5V tolerant)
NRD
in
33
Read enable signal (Low Active) (5V tolerant)
DATA7
I/O
34
Data bus (5V tolerant)
DATA6
I/O
35
Data bus (5V tolerant)
DATA5
I/O
36
Data bus (5V tolerant)
DATA4
I/O
37
Data bus (5V tolerant)
DATA3
I/O
38
Data bus (5V tolerant)
DATA2
I/O
39
Data bus (5V tolerant)
VSSQ
-
40
GND (For ASIC I/O)
VDDQ
-
41
Power Supply (3.3V: For ASIC I/O)
DATA1
I/O
42
Data bus (5V tolerant)
DATA0
I/O
43
Data bus (5V tolerant)
NCS1
in
44
Chip select signal (Low Active) (internal pull up)
NCS0
in
45
Chip select signal (Low Active) (internal pull up)
DEC_NOCS1
out
46
DECODE result (Low Active)
DEC_NOCS0
out
47
DECODE result (Low Active)
DEC_NCSI
in
48
Chip select signal (Low Active) of Address decoder (equivalent to
139) (internal pull up)
139) (internal pull up)
DEC_AD/ADD5
in
49
Address (Low Active) of Address decoder (equivalent to 139)
(internal pull up)
It becomes the input terminal of ADD 5 at the extension mode.
(internal pull up)
It becomes the input terminal of ADD 5 at the extension mode.
ADD4
in
50
Address bus (5V tolerant)
ADD3
in
51
Address bus (5V tolerant)
ADD2
in
52
Address bus (5V tolerant)
VSS
-
53
GND (For internal ASIC)
VDD
-
54
Power Supply (2.5V: For internal Power of ASIC)
ADD1
in
55
Address bus (5V tolerant)
ADD0
in
56
Address bus (5V tolerant)
CLK_EN
in
57
System clock select terminal for ASIC shipment inspection (Normal
“H” input) (5V tolerant)
“H” input) (5V tolerant)
NRST
in
58
System reset (Low Active) (Schmidt trigger input) (5V tolerant)
VDDQ
-
59
Power Supply for ASIC I/O (3.3V)
VSSQ
-
60
GND for ASIC I/O
PLL_VCNT
in
61
Bias voltage for internal PLL
PLLVSS
-
62
GND for internal PLL
PLLVDD
-
63
Power Supply for internal PLL (2.5V)
DT_STD3
out
64
Outside line mode: DTMF detection status (High Active) *not used
DT_STD2
out
65
Outside line mode: DTMF detection status (High Active) *not used
DT_STD1
out
66
Outside line mode: DTMF detection status (High Active) *not used
DT_STD0
out
67
Outside line mode: DTMF detection status (High Active) *not used
VDD
-
68
Power Supply (2.5V: For internal Power of ASIC)
VSS
-
69
GND (For internal ASIC)
OSI
in
70
Crystal departure pendulum input terminal (4.096MHz)
OSO
out
71
Crystal departure pendulum output terminal (4.096MHz)
VSSQ
-
72
GND for ASIC I/O
TST_CLK
in
73
Clock input for factory inspection (normal “H” input) (5V tolerant)
SCAN_EN
in
74
Scan mode enable (normal “L” input) (5V tolerant)
DT_TOE3/HWF
H
H
in
75
Outside line mode : DTMF output enable
Extension mode : HW frame head (8kHz) <TDA30 mode> (5V
tolerant)
Extension mode : HW frame head (8kHz) <TDA30 mode> (5V
tolerant)
DT_TOE2/HWC
P
P
in
76
Outside line mode : DTMF output enable
Extension mode : HW channel pulse <TDA100/200/600 mode>
(5V tolerant)
Extension mode : HW channel pulse <TDA100/200/600 mode>
(5V tolerant)
DT_TOE1/HWC
LK
LK
in
77
Outside line mode : DTMF output enable
Extension mode : HW clock (4.096MHz or 2.048MHz) (5V tolerant)
Extension mode : HW clock (4.096MHz or 2.048MHz) (5V tolerant)
DT_TOE0/UHW
D
D
I/O
78
Outside line mode : DTMF output enable
Extension mode : Going up HW data (5V tolerant)
Extension mode : Going up HW data (5V tolerant)
VDDQ
-
79
Power Supply for ASIC I/O (3.3V)
VSSQ
-
80
GND for ASIC I/O
PDATA/PIO7
I/O
81
The serial data for Pay Tone detection IC setting (5V tolerant)
PCLK/PIO6
I/O
82
Clock for Pay Tone setting (5V tolerant)
NPCS1/PIO5
I/O
83
Chip select signal for Pay Tone seting (5V tolerant)
NPCS0/PIO4
I/O
84
Chip select signal for Pay Tone seting (5V tolerant)
PDET3/PIO3
I/O
85
Detection signal of Pay Tone (5V tolerant)
PDET2/PIO2
I/O
86
Detection signal of Pay Tone (5V tolerant)
PDET1/PIO1
I/O
87
Detection signal of Pay Tone (5V tolerant)
PDET0/PIO0
I/O
88
Detection signal of Pay Tone (5V tolerant)
VDD
-
89
Power Supply (2.5V: For internal Power of ASIC)
VSS
-
90
GND (For internal ASIC)
11
KX-TDA3168XJ / KX-TDA3168X
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