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8 IC DATA
8.1. IC1
Signal Name
I/O
Pin No.
DESCRIPTION
nRST
I
60
Reset
D7-0
I/O
10, 8-2
Data-bus from host CPU
A4-0
I
95-99
Address-bus from host CPU
nCS
I
18
Chip select signal from host CPU
nRD
I
19
Read signal from host CPU
nWR
I
16
Write signal from host CPU
nINT
O
21
Interrupt signal for host CPU
C_CLK_A
O
69
Clock signal (C-BUS interface) (Block_A)
C_CLK_B
O
74
Clock signal (C-BUS interface) (Block_B)
C_SD_A
O
66
Serial data output signal (C-BUS interface) (Block_A)
C_SD_B
O
73
Serial data output signal (C-BUS interface) (Block_B)
C_RD_A
I
59
Serial data receive signal (C-BUS interface) (Block_A)
C_RD_B
I
72
Serial data receive signal (C-BUS interface) (Block_B)
C_nCS_A
O
58
Chip select signal (C-BUS interface) (Block_A)
C_nCS_B
O
71
Chip select signal (C-BUS interface) (Block_B)
C_nREQ_A
O
57
Interrupt signal from Modem IC (Block_A)
C_nREQ_B
O
70
Interrupt signal from Modem IC (Block_B)
C4M
I
11
Highway clock input signal (4.096MHz)
FH
I
22
Highway frame signal (4.096MHz)
CP0
O
90
Not used
CP1
O
91
Not used
MS_CPi
I
92
CODEC timing signal_0
MS_CPo
O
93
CODEC timing signal_1
P07-00
I/O
34-27
Parallel I/O
P17-10
I
84-77
Input port
HWCLK
O
85
Highway clock output signal (4.096MHz)
17
KX-TDA0168XJ / KX-TDA0168X
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