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KX-TDA0156CE
4.2.6.
Power Supply Circuit
6.7V, 4.9V, PA_V3.3V, 3.2V, RF2.5V, RF1.8V, 1.8V and 1.5V are generated in CS.
6.7V is output of DC/DC Convertor. Other power supplies except 3.2V and 1.8V, RF1.8V are made from 6.7V by each regura-
tors.
4.9V is the power supply of DNIC(IC106).
PA_V3.3V and RF2.5V, RF1.8V are the power supply for RF block.
3.2V is the power supply for logic circuit.
1.8V is the power supply for BBIC(IC100).
1.5V is used as the power supply of FPGA(IC103) internal core.
6.7V is output of DC/DC Convertor. Other power supplies except 3.2V and 1.8V, RF1.8V are made from 6.7V by each regura-
tors.
4.9V is the power supply of DNIC(IC106).
PA_V3.3V and RF2.5V, RF1.8V are the power supply for RF block.
3.2V is the power supply for logic circuit.
1.8V is the power supply for BBIC(IC100).
1.5V is used as the power supply of FPGA(IC103) internal core.
4.2.6.1.
Input Filter, Diode Bridge
Input filter for noise rejection and diode bridge for misconnection protection.
4.2.6.2.
DC/DC Start Up Control Circuit
This circuit controls the DC/DC converter for prompt return from the power interruption start-up.
And when the power supply is low voltage, This circuit controls ON/OFF of the DC/DC converter by DIPSW(SW100)
And when the power supply is low voltage, This circuit controls ON/OFF of the DC/DC converter by DIPSW(SW100)
4.2.6.3.
DC/DC Converter Circuit
Generate 6.7V from DC40V power supply.
4.2.6.4.
Power Back Up Circuit
All power supply is backed up by the electric double layer capacitor.
4.2.7.
Clock Circuit
Three kinds of clock are used in CS.
4.2.7.1.
BBIC Clock
10.368MHz crystal oscillator is used.
4.2.7.2.
FPGA Clock
16.384MHz crystal oscillator is used.
4.2.7.3.
DNIC Clock
10.24MHz crystal oscillator is used.
4.2.8.
Reset Circuit
The output signal of reset IC is generated with the detection of 6.7V power supply.
BBIC reset signal(BB_RSTN) is made from reset IC output and the configuration completion status signal of FPGA.
FPGA is reset by the port output from BBIC(IC100).(F_RST)
BBIC reset signal(BB_RSTN) is made from reset IC output and the configuration completion status signal of FPGA.
FPGA is reset by the port output from BBIC(IC100).(F_RST)
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