Read Panasonic KX-TDA0156CE Service Manual online
7
KX-TDA0156CE
4.2.4.
FPGA
FPGA (IC103) has the following features.
(1) MPU i/f
MPU i/f module has the address decoder and the data I/O control part, and controls the access between CPU and internal mod-
ule.
ule.
(2) ST-BUS I/F
ST-BUS i/f module controls Serial communications with DNIC, extractes to D channel, C channel(HK bit), and B channel from
the serial data, and this block is distributed these datas to an internal each module.
Moreover, Dch, Cch, and Bch that come from an internal each module are united, and this module outputs it to DNIC by the ST-
BUS format.
the serial data, and this block is distributed these datas to an internal each module.
Moreover, Dch, Cch, and Bch that come from an internal each module are united, and this module outputs it to DNIC by the ST-
BUS format.
(3) Superframe detection, delay compensation
Detects superframe synchronisation signal from HK bit in the ST-BUS digital data and compensates time difference of delay
caused by the different cable length from CSIF card, then provides it to PSYNC pin of BBIC(IC100).
caused by the different cable length from CSIF card, then provides it to PSYNC pin of BBIC(IC100).
(4) HDLC controller
HDLC is the abbreviation of High level Data Line Control, means a protocol for highly reliable data communication.
D channel data from ST-BUS i/f is transmitted to/from CPU through this module.
D channel data from ST-BUS i/f is transmitted to/from CPU through this module.
(5) BBIC PCM I/F
Extracts voice data from ST-BUS digital data and changes format to BBIC PCM format, then provides it to BBIC(IC100).
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