Read Panasonic KX-NS8290CE Service Manual online
12
KX-NS8290
4.4.
CPU BUS Interface Block Diagram
CPU (M82334) has the function to generate chip select signals, and each device is connected as below diagram.
Remark 1): NAND-Flash is accessed by the function of 'Direct Access Register' which is including in CPU (M82334) and access
timing is controlled by NAND software driver.
Remark 2): Framer (PEF2256H) is connected to UEXP CS4 (16bit) bus, but only low 8bits are used.
timing is controlled by NAND software driver.
Remark 2): Framer (PEF2256H) is connected to UEXP CS4 (16bit) bus, but only low 8bits are used.
4.5.
Interrupt FUnction
CPU (M82334) can handle several external interrupt signals as below.
Chip Select
Device
Addressing Area
Bus Size
DDR CS0
1Gbit DDR2 SDRAM x 2
256MB
16
NT5TU128M8GE-AC
(Max 512MB)
UEXP CS5
512MB NAND Flash ROM
512MB
Remark 1)
TC58NVG2S3ETAI0B3H
UEXP CS4
Framer
64kB
16
PEF2256H
Remark 2)
UEXP CS3
Not Used
UEXP CS2
4MB NOR Flash ROM
4MB
16
S29GL032N90TFI030
UEXP CS1
Not Used
UEXP CS0
Not Used
Pin Assign
Function
Signal Name
Int Configuration
GPIO0
B7
Power Down Alarm Interrupt
PND_n
Positive Edge
GPIO2
C8
RTC Interval Interrupt
RTC_INT_n
Positive Edge
GPIO3
A8
PRI/E1 Framer Interrupt
PEF2256_INT_n
Level Active High
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