Read Panasonic KX-NS500RU (serv.man2) Service Manual online
106
KX-NS500RU
R4
VCC(IO)
-
VCC
R5
HCK_CPU
-
(reserved)
R6
DHW_CPU
O
DOWN high way to CPU
R7
UHW_CPU
I
UP High way from CPU
R8
VCCINT
-
VCC
R9
GND
-
GND
R10
VCCINT
-
VCC
R11
GND
-
GND
R12
VCCINT
-
VCC
R13
GND
-
GND
R14
CDC_DO
O
RMT card CODEC data
R15
CDC_CK_O
O
RMT card CODEC clock
R16
NC
-
No Connection
R17
NIRQ_EXT_I[1]
I
IRQ from BASE card
R18
HWCLK[2]
O
High Way clock output
R19
HWCLK[3]
O
High Way clock output
R20
NCS_BASE_O
O
BASE card CPU bus chip select
R21
HWCLK[6]
O
High Way clock output
R22
HWCLK[5]
O
High Way clock output
T1
CLK24M
I
CPU clock(24MHz)
T2
GND+
I
GND
T3
GPIO0[1]
I/O
SERIAL DSR
T4
HWCLK[7]
O
High Way clock output
T5
NC
-
No Connection
T6
VCCA
-
VCC
T7
FSYNC[7]
O
frame sync output
T8
MC_UHW_O[3]
I
UP High Way from EXP card
T9
NETREF_I[3]
I
NETREF from EXP card
T10
NETREF_I[2]
I
NETREF from EXP card
T11
MC_DHW_O[0]
O
DOWN High Way to EXP card
T12
NC
-
No Connection
T13
NC
-
No Connection
T14
NC
-
No Connection
T15
CDC_CS_O
O
RMT card CODEC chip select
T16
CDC_DI
I
RMT card CODEC data
T17
PT_TXB_O[1]
O
DPT#0 output data
T18
PT_TXB_O[0]
O
DPT#0 output data
T19
VCC(IO)
-
VCC
T20
GND
-
GND
T21
GND+
I
GND
T22
GND+
I
GND
U1
NRST_I
I
FPGA reset
U2
NIRQ_O[1]
O
INT(FPGA#1)
U3
GND
-
GND
U4
VCC(IO)
-
VCC
U5
GNDA
-
GND
U6
VCC(PLL)
-
VCC
U7
NC
-
No Connection
U8
NC
-
No Connection
U9
MC_DHW_O[3]
O
DOWN High Way to EXP card
U10
NC
-
No Connection
U11
NC
-
No Connection
U12
NC
-
No Connection
U13
NC
-
No Connection
U14
UHW_RMT
I
UP High Way from RMT card
U15
NC
-
No Connection
U16
NC
-
No Connection
U17
NC
-
No Connection
U18
VCCA
-
VCC
U19
PT_RXA_I[1]
I
DPT#0 data input
U20
PT_RXA_I[0]
I
DPT#0 data input
U21
HWCLK[1]
O
High Way clock output
U22
HWCLK[0]
O
High Way clock output
V1
NC
-
No Connection
V2
NC
-
No Connection
V3
NC
-
No Connection
V4
NC
-
No Connection
Pin No
Pin Name
I/O
Function
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