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8
KX-NS0180X
4.2.
Circuit Operation
4.2.1.
Description of Control System Circuits
4.2.1.1.
Reset
On startup, releasing the FPGA reset is executed by MAIN Card.
After releasing the FPGA, the local reset signal should be sent to CODEC,CIDA and SLIC by releasing the soft rest from MAIN
Card, and CODEC factor should be downloaded from MAIN Card.
After releasing the FPGA, the local reset signal should be sent to CODEC,CIDA and SLIC by releasing the soft rest from MAIN
Card, and CODEC factor should be downloaded from MAIN Card.
4.2.1.2.
Local Highway Interface
Packs 2.048, 4.096, 8.192 MHz highway (Max.64 timeslot). (voice communication bus in the circuit board)
The PCM data of arbitrary streams 0-15 (128 timeslot / 1 stream) on the CT bus can switch to the arbitrary local highway (64
timeslot) by the local TSW.
The timeslot configuration example of the local highway is shown below.
The PCM data of arbitrary streams 0-15 (128 timeslot / 1 stream) on the CT bus can switch to the arbitrary local highway (64
timeslot) by the local TSW.
The timeslot configuration example of the local highway is shown below.
TS No.
PCM data
TS No.
PCM data
96
PRI30/BRI/LCOT#1
112
PRI23#16/PRI30#16
97
PRI23#1/PRI30/BRI/LCOT#2
113
PRI23#17/PRI30#17
98
PRI23#2/PRI30/BRI/(LCOT)#3
114
PRI23#18/PRI30#18
99
PRI23#3/PRI30/BRI/(LCOT)#4
115
PRI23#19/PRI30#19
100
PRI23#4/PRI30/BRI/(LCOT)#5
116
PRI23#20/PRI30#20
101
PRI23#5/PRI30/BRI/(LCOT)#6
117
PRI23#21/PRI30#21
102
PRI23#6/PRI30/BRI/(LCOT)#7
118
PRI23#22/PRI30#22
103
PRI23#7/PRI30/BRI/(LCOT)#8
119
PRI23#23/PRI30#23
104
PRI23#8/PRI30#9
120
PRI23#24/PRI30#24
105
PRI23#9/PRI30#10
121
PRI30#25
106
PRI23#10/PRI30#11
122
PRI30#26
107
PRI23#11/PRI30#12
123
PRI30#27
108
PRI23#12/PRI30#13
124
PRI30#28
109
PRI23#13/PRI30#14
125
PRI30#29
110
PRI23#14/PRI30#15
126
PRI30#30
111
PRI23#15
127
FAX#0
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