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8
KX-NS0154CE
4.5.
Clock Circuit
4.5.1.
System Clock
Main system clock (13.824MHz) is generated from X501, and Oscillation circuit consists of X501 and IC501.
This clock is used for basic clock of IC501's all internal clock and RF.
This clock is supplied to IC100 and IC503 via buffer IC (IC704).
This enables synchronization among IC100, IC501 and IC503.
X201 is used by IC100 during its boot sequence and basic clock for PLLIC (IC301).
This clock is used for basic clock of IC501's all internal clock and RF.
This clock is supplied to IC100 and IC503 via buffer IC (IC704).
This enables synchronization among IC100, IC501 and IC503.
X201 is used by IC100 during its boot sequence and basic clock for PLLIC (IC301).
4.5.2.
PLLIC
PLLIC (IC302) is controlled by IC100 with I2C bus.
PLLIC generate 12MHz and 25MHz clock.
12MHz is supplied to IC100 and used for USB circuit for maintenance.
25MHz is supplied to PHY for Ethernet communication.
PLLIC generate 12MHz and 25MHz clock.
12MHz is supplied to IC100 and used for USB circuit for maintenance.
25MHz is supplied to PHY for Ethernet communication.
4.6.
Memory Access Circuit
4.6.1.
IC100
IC100 (DVF99) has separated memory access port for NAND Flash memory (IC102) and DDR2 SDRAM (IC101).
The program for IC100 has been stored in IC102.
The program for IC100 has been stored in IC102.
4.6.2.
IC501 and IC503
IC501(DCX81 for RF) and IC503 (DCX81 for DSP) have the QSPI Serial Flash access port.
The program for IC501 has been stored in IC502, and the program for IC503 has been stored in IC504.
The program for IC501 has been stored in IC502, and the program for IC503 has been stored in IC504.
4.7.
Ethernet Circuit
Ethernet signals from JK302 are transfered to IC302(PHY) through T301.
IC302 transfers singal to DVF99(IC100)
IC302 transfers singal to DVF99(IC100)
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