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18
KX-NS0110X/KX-NS0111X/KX-NS0112X
9.1.2.
No. 2
(1)
(2)
(3)
(4)
(5)
(6)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(9)
(10)
(11)
(12)
(11)
(12)
(13)
KX-NS0110X MII for DSPO BOARD No.2 1/2
C
E
B
A
D
F
3
4
2
1
MII0_RXD0[0-3]
MII0_TXD0[0]
MII0_RXD0[2]
MII0_RXD0[1]
MII0_TXD0[1]
MII0_RXD0[0]
MII0_RXD0[3]
MII0_TXD0[0-3]
MII0_TXD0[3]
MII0_TXD0[2]
MII1_TXD[0-3]
MII1_RXD[0-3]
MII1_RXD[0]
MII1_RXD[1]
MII1_RXD[2]
MII1_RXD[3]
MII1_RXD[1]
MII1_RXD[2]
MII1_RXD[3]
MII1_TXD[0]
MII1_TXD[1]
MII1_TXD[2]
MII1_TXD[3]
MII1_TXD[1]
MII1_TXD[2]
MII1_TXD[3]
IC101
B1 JTAGMODE1
W3 TCK
W5 TRST_N
W1 TMS
Y4 TDI
Y3 TDO
A21 Reserved5
B6 Reserved6
N19 AVDD_CORE0
N20 AVDD_CORE2
N21 AVDD_CORE1
A16 Reserved7
R4 Reserved8
E4 UART_TX0
E2 UART_RX0
AA1 UART_TX1
Y2 UART_RX1
C19 I2C_SCL
C20 I2C_SDA
Y1 SPI0_SCLK
V4 SPI0_TXD
V2 SPI0_RXD
V3 SPI0_SS0_N
V1 SPI0_SS1_N
U4 SPI0_SS2_N
U2 SPI0_SS3_N
A5 SPI1_SCLK
D6 SPI1_TXD
D4 SPI1_RXD
A3 SPI1_SS0_N
B5 SPI1_SS1_N
C5 SPI1_SS2_N
D5 SPI1_SS3_N
N1 TDM0_CK
M4 TDM0_FS
N2 TDM0_DR
N3 TDM0_DX
D1 TDM0_SR
C1 TDM0_SX
M1 TDM1_CK
L4 TDM1_FS
M2 TDM1_DR
M3 TDM1_DX
D2 TDM1_SR
E3 TDM1_SX
U20 RESET_N
U21 REFCLK
W22 Reserved9
B22 OPMODE0
L1
MII0_RXD0
C21 OPMODE1
C2 EROM_N
C22 PLLBYPASS_N
Y21 BSCANMODE_N
W21 BISR_N
A22 TRISTATE_N
B20 ARAMBOOT_N
L2
MII0_RXD1
H1
MII0_RXD2
H2
MII0_RXD3
F4
Reserved
F2
Reserved
F3
Reserved
N4
Reserved
K4
MII0_RX_CLK
L3
MII0_RX_DV
H4
MIIO_CRS
J3
MII0_COL
K1
MII0_RX_ER
J1
MII0_TXD0
J2
MII0_TXD1
G1
MII0_TXD2
G4
MII0_TXD3
F1
GMII0_STRAP3
W2
Reserved
U3
Reserved
G3
Reserved
E1
Reserved
J4
MII0_TX_EN
G2
MII0_TX_ER
D22
Reserved
V19
GMII0_STRAP0
V20
GMII0_STRAP1
H3
MII0_TX_CLK
D14
MII1_RXD0
A13
MII1_RXD1
B13
MII1_RXD2
C13
MII1_RXD3
D10
Reserved
C10
Reserved
B10
Reserved
A10
Reserved
A12
MII1_RX_CLK
A11
MII1_RX_DV
A9
MII1_CRS
C11
MII1_COL
C12
MII1_RX_ER
B14
MII1_TXD0
C14
MII1_TXD1
B15
MII1_TXD2
C15
MII1_TXD3
B11
GMII1_STRAP3
D12
Reserved
B12
Reserved
D13
Reserved
D11
Reserved
D15
MII1_TX_EN
A15
MII1_TX_ER
D8
TBI1_EWRAP
B18
GMII1_STRAP0
A20
GMII1_STRAP1
A14
MII1_TX_CLK
K2
MII_MDC
K3
MII_MDIO
U1
PHY_REFCLK
P3
SGMII_REFCLK_POS
P4
SGMII_REFCLK_NEG
R3
SGMII_REXT
T3
SGMII_TX0_POS
T4
SGMII_TX0_NEG
T2
SGMII_RX0_POS
T1
SGMII_RX0_NEG
P2
SGMII_TX1_POS
P1
SGMII_TX1_NEG
R1
SGMII_RX1_POS
R2
SGMII_RX1_NEG
DG
+3.3VD
+3.3VD
R230
100
R216
100
+1.05VD_DSP0
R215
100
DG
R229
100
+3.3VD
R228
100
C210
10u
10
C211
0.1u
16
C212
0.01u
16
C207
10u
10
C209
0.01u
16
C208
0.1u
16
C206
0.01u
16
C203
10u
10
C204
0.1u
16
DG
L201
L202
L203
DG
R205
33
R218
100
R219
100
R220
100
R227
100
1
2
3
4
2
3
4
5
6
7
8
R226
100
1
2
3
4
2
3
4
5
6
7
8
R222
47
R221
100
MII1_TX_CLK 005:5C
MII1_RX_DV
005:5B
MII1_RX_ER
005:5C
MII1_RXD[0-3]
005:5B
MII1_RX_CLK_1 005:5B
DG
R214
100
DG
R212
1k
R213
1k
R217
0
NC
C202
0.1u
16
R207
10k
NC
TDM0_DR_DSP
001:8B
R210
47
R211
47
TDM01_DL
005:1D
R203
10k
NC
CLK_25MHz
005:1D
R204
33
TDM1_DR_DSP
001:9D;005:1D
*R201
0
_
*R202
0
_
*R294
100
_
1
2
3
4
2
3
4
5
6
7
8
DG
*R291
100
_
*R292
100
_
*R293
100
_
*R225
33
NC
*R223
33
NC
R224
330
*R260
180
NC
*R231
33
NC
R209
0
NC
X202
25M
NC
1 OE
2 GND
3
OUT
4
VDD
DG
+3.3VD
C205
0.1u
16
NC
R208
0
NC
IC201
1 NC
2
A
4
Y
5
VCC
3 GND
C219
0.1u
16
DG
+3.3VD
R259
0
DL202
NC
1
2
3
DL201
1
2
3
X201
25M
1 OE
2 GND
3
OUT
4
VDD
*R258
33
CLK_25MHz
TMS_DSP0
BSCANMODE_N_DSP0
TRISTATE_N_DSP0
RX0_DSP0
JTAGMODE1_DSP0
TCK_DSP0
TX0_DSP0
TRST_N_DSP0
TDI_DSP0
TDO_DSP0
TDO_DSP0
nRST_DSP
003:5B;005:1D
MII1_TXD[0-3] 005:5C
MII1_TX_ER
005:5C
MII1_TX_EN
005:5C
nRST_PORT_PHY
001:8E
TDM0_DX_DSP
001:8B
TDM10_DL
005:1D
TDM1_DX_DSP
001:9D;005:1D
MII1_RX_CLK_2 005:5B
TDM0_CK_DSP
001:8B;005:1D
TDM0_FS_DSP
001:8B;005:1D
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
For PLL AVDD
Shared 100 pull-down to GND
Shared 100 pull-down to GND
Shared 100 pull-down to GND
NC
NC
NC
NC
NC
NC
NC
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