KX-NCV200BX, KX-TVM204X, KX-TVM296X (serv.man3) - Panasonic PBX Service Manual (repair manual). Page 117

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• PBX Interface

Related output/input signal: 
PDR (PDR0, PDR1 1), PVRH, PVRL, PDX0, PDX1
DDR (DDR0, DDR1), DVRH, DVRL, DDX0, DDX1
Related register name: 
P_RST, PBXMD, PBXIF, D_RST, DPTMD, DPTIF
With a 512Kbps ping-pong transmission (AMI encoding) interface, a transmission band of 2B (64kbps x 2) + D (16Kbps) +C
(8Kbps) is ensured. It also has the following functions: clock extraction through digital PLL, synchronization switching, DPT
interface, transmitted pulse width programmability, and receiving edge position programmability.

• Transmission frame format

The frame format on the transmission path is as shown in Fig.3-4: Frame timing; and transmissions are performed for each bit
shown in Table 3-1: Information field explanation table. Receiving operation from the PBX is performed, and after 1 bit time has
elapsed transmission operation is performed. After the parity bit is transmitted, an idle time of 7 bit times is commenced.
One bit time is 512KHz (1.95

µs), and the information encoding used is AMI.

Table 3-1: Information Field Explanation

Table 3-2: AMI Encoding Rules

PDX0,PDX1,DDR0,DDR1,DDX0 and DDX1 performs similar controls.

Field name

Bit number

Explanation

SYNC

5

Continuous [00000] pattern; used for clock extraction by PLL.

MAM

3

A [000] pattern (01-01-10) violating the AMI encoding side; used to detect the header of the
received frame.

C

1

Valid data inverted from B1 channel. 

2

D

2

Valid data inverted from B2 channel

B1

8

Parity data, transmitted to PDX0/DDX0 line and PDX1/DDX1 line.Parity is added so that the num-
ber of 0 patterns becomes equal.Combined with bit ensuring direct current balance on the line.

B2

8

Continuous [00000] pattern; used for clock extraction by PLL.

P

1

A [000] pattern (01-01-10) violating the AMI encoding side; used to detect the header of the
received frame.

Voltage Level

PDR

Normal (PACT=0)

Inversion (PACT=1)

Information Bit

PDR0

PDR1

PDR0

PDR1

+1.75V

1

1

0

0

1

0V

1

0

0

1

0

+3.3V

0

1

1

0

0

-

0

0

1

1

Prohibited