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7
KX-NCP1188XJ
4.2.
Circuit Operation
4.2.1.
CPU Peripheral Circuit
The CPU (IC1) is a single chip microcomputer of RISC architecture.
This item describes a memory interface (program & work) and peripheral functions.
This item describes a memory interface (program & work) and peripheral functions.
4.2.1.1.
Memory (Program & Work)
4.2.1.2.
Chip Select Logic
Part Name
Size
Purpose
Remarks
Flash
(IC5)
(IC5)
4Mbit
(256K x 16)
(256K x 16)
Program Area
Flash memory is employed for the software downloading by on-board.
SRAM
(IC3)
(IC3)
4Mbit
(256K x 16)
(256K x 16)
Work Area
Terminals
Function used
Wait Function
(Numeral is no. of
clocks.)
Remarks
CS Terminals
Individual Output
(1)
Individual Output
(2)
nCS0 (area 0)
-
-
nCS0
1+Programable
or
1+Programable+WAIT
Terminals
Terminals
Used for Flash memory CS.
nCS1 (area 1)
nCASH (DRAM)
-
nCS1
Read 1/Write 2 or
2+WAIT Terminals
2+WAIT Terminals
Used for ASIC (IC2) (ASIC) CS
nCS2 (area 2)
-
-
nCS2
1+Programable
or
1+Programable+WAIT
Terminals
Terminals
Used for SRAM (Basic) CS. Work
Area
Area
nCS3 (area 3)
nCASL (DRAM)
-
nCS3
Read 1/Write 2 or
2+WAIT Terminals
2+WAIT Terminals
CS Reserve
nCS4 (area 4)
PA0 (I/O)
TIOCA0 (Timer)
nCS4
Read 1/Write 2 or
2+WAIT Terminals
2+WAIT Terminals
CS Reserve
nCS5 (area 5)
PA1 (I/O)
nRAS (DRAM)
nCS5
Read 1/Write 2 or
2+WAIT Terminals
2+WAIT Terminals
CS Reserve
nCS6 (area 6)
PA2 (I/O)
TIOCB0 (Timer)
nCS6
1+Programable
or
1+Programable+WAIT
Terminals
Terminals
Used for peripheral LSI CS.
Used for framer IC, DSP CS.
Used for framer IC, DSP CS.
nCS7 (area 7)
PA3 (I/O)
nWAIT
nWAIT
Read 1/Write 2 or
2+WAIT Terminals
2+WAIT Terminals
Used for Input Wait Terminals.
Chip Select
Address
Device Bit Wide
Assignment
Device
Bus Cycle
Remarks
nCS0
0000000h
l
0FFFFFFh
l
0FFFFFFh
16bit
4M_Flash
(IC 5)
(IC 5)
2 Clock (1+Long Wait1)
Port allocation of word by static bus sizing
Bus cycle has same setting as Area 2
(nCS2).
Bus cycle has same setting as Area 2
(nCS2).
nCS1
1000000h
l
1FFFFFFh
l
1FFFFFFh
8bit
ASIC (IC2)
2+WAIT Terminals
Port allocation of byte by static bus sizing.
nCS2
A000000h
l
AFFFFFFh
l
AFFFFFFh
16bit
4M_SRAM
(IC 3)
(IC 3)
2 Clock (1+Long Wait1)
Port allocation of word by static bus sizing
Bus cycle has same setting as Area 0
(nCS0).
Bus cycle has same setting as Area 0
(nCS0).
nCS6
6000000h
l
6FFFFFFh
l
6FFFFFFh
8bit
E1_IC
(IC302)
(IC302)
3 Clock (1+Long Wait2)
Port allocation of byte by static bus sizing.
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