KX-NCP1172XJ - Panasonic PBX Service Manual (repair manual). Page 7

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     KX-NCP1172XJ
5.2.
Circuit Operation
5.2.1.
Control-System Circuit
5.2.1.1.
ASIC Peripherals
• SRAM (1Mbit)......IC504
Used for the data buffer for CPU work area, and PT communication.
• Dual port RAM (128byte)......Uses a part of the functions of IC1.
Used for the buffer for the communications with MPR.
• Reset
On boot-up, ASIC reset release is carried out by EC_nRST from MPR. After the ASIC reset release, CPU reset is released by
the soft reset release from MPR; then, LPR program starts up.
• Operation in instantaneous interruption
When instantaneous power interruption is 300msec or less, reset operation is not carried out because the voltage is retained by
the capacitor in the power supply
However, for the purpose of reducing the power consumption during instantaneous interruption, if it is detected (nHALT=L),
power down mode is established and CPU itself goes into sleep mode. CPU sleep is recovered from by the edge detection of
nIRQ0 
→ L.
• LED Operation status indicating LED (Two colors)
Red ON: Fault (RESET included)
Green ON: INS (Line not in use)
Green Flash (60/minute): INS (Line in use)
Red blinking: OUS
OFF: Power supply failure
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