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9 Block Diagrams
9.1. OVERALL BLOCK DIAGRAM
VW-BN1PP/E/GK
OVERALL BLOCK DIAGRAM
OVERALL BLOCK DIAGRAM
TRAVERSE
MOTOR
MOTOR
LOADING
MOTOR
MOTOR
RESET B
V BUS
RS DM
DM
DP
RS DP
+3.3V
+5V
+3.3V
+D2.5V
B2-
IC4001-
,
+3.3V
+3.3V
Q4004
Q4001
Q1101
Q1001
(RESET)
IC4003
4
5
OUT
VDD
(REGULATOR)
IC1301
4
5
V OUT
GND
VCC
(DC-DC CONVERTER)
IC1201
6
3
SW
4
GND
5
P GND
EN
7 PVCC
8 VCC
8 VCC
1 ADJ
V CONT
(RESET)
IC1001
4
2
OUT
VDD
IC9001
(EEPROM)
IC4001
SDA
GND
IDE A2
IDE A1
IDE A0
IDE RESET
20
22
21
53
IDE D3
IDE D2
IDE D1
IDE D0
43
38
36
34
IDE D7
IDE D6
IDE D5
IDE D4
52
50
47
45
IDE D11
IDE D10
IDE D9
IDE D8
44
46
48
51
IDE D15
IDE D14
IDE D13
IDE D12
33
35
37
42
IC4002
(USB-ATAPI BRIDGE)
59
19
,
8
IC4002-
,
3
,
26
,
39 58
+A2.5V
IC4002-
,
11 15
IC4002-
,
7
,
24
,
,
41
54
IC4003- 5
,
20
,
21
,
30
,
31 32
SDA
60
SCL
61
CD
DVD
OPTICAL PICK-UP
FEP
(FRONT END PROCESSOR)
(FRONT END PROCESSOR)
LASER
DIODE
DRIVE
(LDD)
DIODE
DRIVE
(LDD)
RF
BLOCK
BLOCK
SERVO
BLOCK
BLOCK
THERMISTOR
DETECTOR
LASER
DETECTOR
LASER
MOTOR
SPINDLE
MOTOR
DRIVE
(SPINDLE &
ACTUATOR)
DRIVE
(SPINDLE &
ACTUATOR)
MOTOR
DRIVE
(LOADING)
DRIVE
(LOADING)
(SUPER OPTICAL DISC CONTROLLER)
SODC
DVD DRIVE UNIT
DRAM
CONTROLLER
CONTROLLER
DRC
ADSC
SERVO
I/O
I/O
CPU
(32bit)
(32bit)
SDRAM
(16Mbit)
(16Mbit)
FLASH
ROM
(16Mbit)
ROM
(16Mbit)
SYSTEM I/F,
WRITE
STRATEGY
WRITE
STRATEGY
ATAPI
INTERFACE
INTERFACE
4
5
SCL
A2
3
6
WP
NC
2
7
VCC
NC
1
8
Q1102
D
S
4
1
D 2
D 4
D
D 4
D
G
3
6
Q1103
D
S
4
1
D 2
D 4
D
D 4
D
G
3
6
4
1
3
2
2
1
3
4
5
(USB)
GND
NC
D+
D-
V BUS
JK9001
3
4
2
(DC IN)
JK1001
IP1
6
5
8
9
17
48
5
34
33
35
31
17
34
B2
B3
B1
SUB
SUB
MAIN
3-10,40-47
6-21
B2
B3
B1
SUB
SUB
MAIN
1
2
ACTUATOR
FO/TR
VW-BN1PP / VW-BN1E / VW-BN1GK /
13
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