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S-5
S3.3. Camera Circuit Block Diagram
ASP1 CS
CG SO
CG CLK
CG SO
CG CLK
From IC2006
ASP1 CS
CG SO
CG CLK
CG SO
CG CLK
From IC2006
202
200
195
200
195
CCD IMAGE SENSOR
SIGR
SDR-S100 CAMERA CIRCUIT BLOCK DIAGRAM
281
18
IC303
(DSP)
MNDB0
MNDB15
177
184
YOUT0
YOUT7
165
174
COUT0
COUT7
252
264
IC104
(CDS/PGA&10bit ADC: R)
22
CDS
PGA
SERIAL
I/F
10bit
ADC
35
34
33
D0
1
9
SCK
S
D
ATA
CS
D9
21
BLKFB
CDSIN
23
BLKC
20
BLKSH
27
DC OFFSET
CONPENSATION
CIRCUIT
BIAS
GENERATOR
24
BIAS
29 28 30
OUTPUT
LA
TCH
CIRCUIT
10bit
36
12
ADCLK
VR
T
VRM
VRB
ADCIN
IC105
(CDS/PGA&10bit ADC: G)
22
CDS
PGA
SERIAL
I/F
10bit
ADC
35
34
33
D0
1
9
SCK
S
D
ATA
CS
D9
21
BLKFB
CDSIN
23
BLKC
20
BLKSH
27
DC OFFSET
CONPENSATION
CIRCUIT
BIAS
GENERATOR
24
BIAS
29 28 30
OUTPUT
LA
TCH
CIRCUIT
10bit
36
VR
T
VRM
VRB
ADCIN
IC106
(CDS/PGA&10bit ADC: B)
22
CDS
PGA
SERIAL
I/F
10bit
ADC
35
34
33
D0
1
9
SCK
SDA
TA
CS
D9
21
BLKFB
CDSIN
23
BLKC
20
BLKSH
27
DC OFFSET
CONPENSATION
CIRCUIT
BIAS
GENERATOR
24
BIAS
29 28 30
OUTPUT
LA
TCH
CIRCUIT
10bit
36
VR
T
VRM
VRB
ADCIN
242
251
230
241
RIN0
RIN9
GIN0
GIN9
BIN0
BIN9
IC101
(CG/SSG)
8
SCLK
10
SCS
9
SDATA
5
CFK2I
1/2
FREQUENCY
DIVIDER
SERIAL
DATA INPUT
CIRCUIT
HIGHT-SPEED
PULSE
DECODER
38
42
44
46
43
45
47
60
CH PULSE
DECODER
31
32
33
32
33
V TRANSFER
PULSE
DECODER
27
28
29
30
28
29
30
PROCESS
PULSE
DECODER
11
16
17
18
17
18
V TIMING
S/R
H TIMING
S/R
HCLR
GENERATOR
FI
VD
H REFERENCE
PULSE GENERATOR
54
TVMD
V4
V3
V2
V1
SUB
CH2
CH1
CCDHD
CPOB
ADCLK1
DS2B
DS2R
DS2G
DS1B
DS1R
DS1G
R
H1
H2
24
28
26
23
27
1
25
36
37
37
3
IC110
(HORIZONTAL DRIVER)
IC108
(VERTICAL DRIVER)
CH1
CH2
ISUB
IV1
IV2
IV3
IV4
1
5
11
9
13
12
10
8
H1R
H1G
H1B
3
IC107
(HORIZONTAL DRIVER)
1
5
11
9
13
12
10
8
H2R
H2G
H2B
1
FP6001
4
5
V1RB
V2RB
6
V3RB
7
V4RB
8
H1R
9
H2R
10
SUBR
15
V1G
16
V2G
17
V3G
18
V4G
19
H1G
20
H2G
21
SUBG
22
R
25
SIGG
26
PT
27
PT
30
V1B
31
V2B
32
V3B
33
V4B
34
H1B
35
H2B
36
SUBB
39
SIGB
CKA1 CKA2 CKA3 CKA4
16 OV1
9 OV2
5 OV3
15 OV4
17 OV5
10 OV6
4 OV7
14 OV8
12 OSUB
CKA5
ASP1 CS
CG SO
CG CLK
CG SO
CG CLK
To IC2006
193 FCK
16
17
DS1
DS2
TIMING
GENERATOR
12
ADCLK
16
17
DS1
DS2
TIMING
GENERATOR
12
ADCLK
16
17
DS1
DS2
TIMING
GENERATOR
15
CPOB
15
CPOB
15
CPOB
CCDHD
TVD
FI
TVD
FI
X101
(54MHz)
CG CLK
CG SO
CG CS
From IC2006
TWMD
(From IC2006)
To IC2006/
IC3400
CL103
350
pixels
176
pixels
176
pixels
84
pixels
28
28
pixels
18
pixels
Horizontal
OB
(41 pixels)
84
pixels
28
28
pixels
18
pixels
384
lines
116 lines
116 lines
48 lines
24 lines
8 lines
48 lines
24 lines
24 lines
6 lines
Vertical OB
(12 lines)
ZONE
ZONE
ZONE
ZONE
Horizontal
OB
(4 pixels)
Vertical OB
(11 lines)
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