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2.3. VIDEO BLOCK DIAGRAM
H
H
H
H
H
H
61
SPA
57
HID
56
TSR
96 SPA
93 HID
TSR
97
PB
89
REC/VITON
77
VITON
REC/
PB
64
63
1
LOGIC
INSR
52
Q3201
Q3203
AMP
CIRCUIT
TO MONITOR
Q5006
:ON
PB H2
:ON
PB H1
RA1 OUT
RA2 OUT
PB H1
PB H2
HA1 IN
HA2 IN
MON2 IN
MON1 IN
MON1 IN
MON1 IN
MON2 IN
HA2 IN
HA1 IN
PB H2
PB H1
RA2 OUT
RA1 OUT
2
FP5001
3
FP5001
5
FP5001
4
FP5001
Q5003
AMP
Q5002
AMP
RA2 OUT
RA1 OUT
HSE
ATFI OUT
CL3002
CL3204
ATFI 48
TERMINAL
FROM/TO DV
/TRST
SMP
SSP
134
144
77 COM RDY
COM RDY 12
SBA CS
SBA SCK
SBA SDA
MHz)
(24.576
X3003
91 XI
XO
90
VCOO
64
CL3003
SSP 86
SMP
SSP
VSP
HSP
CL3004
CL3002
18AMP2IN
27AMP2IN
18CLK
27CLK
65
34
32
(27MHz)
X3001
CL3006
18
CDTI
CONTROL BLOCK
REFER TO
FROM IC2011
MIC UNIT
TO
4
3
L IN2
R IN1
SPEAKER
TO
CONNECTOR
MULTI JACK
FROM/TO
AMP
Q3004
Q3003
AMP
CONTROL CIRCUIT
FROM
CONNECTOR
TO MULTI JACK
VBLK
28
Q3001
AMP
Q3002
AMP
INV
119
INH
118
PB VS
77
PB HS
76
CAMERA BLOCK
REFER TO
36
46
SMP
155
52
SSP
148
CONTROL CIRCUIT
FROM
/RST
30
17
105
39
40
15
/CS
16
CCLK
CDTO 17
PC18C
33
42
PC27C
5
40
CAS*VD
3
60
CAS*HD
2
59
(AUDIO I/F)
IC4501
SDTI
SDTO
BCLK
LRCLK
MCLK
12
11
9
10
8
20
21
6
5
L OUT
R OUT
L IN2
R IN2
CLK 18M
CLK 450K
:MAIN SIGNAL PATH IN PLAYBACK MODE
:MAIN SIGNAL PATH IN REC MODE
(16bit)
/DATA
ADDRESS
-
120
103
9
(PC I/F)
IC2011
(DIGITAL I/F)
IC3801
(HR AMP)
IC5001
(EQ)
IC3203
(VITERBI A/D)
IC3204
(EDA MEMORY)
IC3202
(EDA)
IC3201
SDI
SDO
SCK
(16bit)
/DATA
ADDRESS
(CONTROL MICON)
IC2001
X OUT
X IN
47
46
FSSEL1
FSSEL0
FSCLK
CLK18M
CLK27M
CLK18/8M
CLK450K
CLK18M2
Y OUT
C OUT
(AUDIO DSP)
IC4502
HD
EVF
OUT
B-Y
OUT
R-Y
STP1
SCLK
SDIO
STP
SCLK
SDA
DODAT
AIDAT
BCLK
LRCLK
MCLK
78
80
79
93
86
94
96
95
FS1
FS0
VCOI
SHM225
CLK18
67
68
1
16
(4bit)
DATA IN/OUT
LSB
(8bit)
DATA IN/OUT
LSB
(18bit)
ADDRESS OUT
18
37
-
(18bit)
ADDRESS IN
(8bit)
DATA IN/OUT
LSB
CLK18M1
(VCO)
IC3005
61
63
62
(V DRIVE)
IC3006
40
39
46
25
13
33
31
(CAS)
IC3003
(SHUFFLING MEMORY)
(DVIO)
IC3002
IC3001
CH2
CH1
Q5005
/EVR
MULTI JACK CONNECTOR
FROM/TO
A/D
(7bit)
DATA OUT
PB
LSB
11
19
7
10
TO EVR
MON1 IN
MON2 IN
HA2 IN
HA1 IN
PB H2
PB H1
26
34
36
24
32
28
31
29
ATF OUT
(PB DATA)
AGC OUT
57
64
7
AMP
BPF
1+D
TFIL
LPF
EQ
PRE
AMP
LATCH
VCO
41.85M/72
41.85M(REC)
5
4
2
55
56
58
59
18
17
62
53
33
35
11
31
47
50
-
71
70
69
-
139
154
DCS DO
DCS DI
DCS CLK
WA
DCS
STP
DCS
82
83
81
107
108
LSB
(9bit)
ADDRESS OUT
-
LSB
(16bit)
DATA IN/OUT
-
7bit(LP)
PB DATA IN
(SP)
PB DATA
(41.85M)
PB CLK
REF CLK
REC CLK
(REC DATA)
HSE
(16bit)
DATA IN/OUT
LSB
(9bit)
ADDRESS IN
LSB
CLK18M
(16bit)
/DATA
ADDRESS
(4bit)
DATA IN
UART O
UART I
SDO
SDI
SCK
51
50
80
79
76
142
72
69
120
102
133
130
-
--
-
-
-
64
47
2
1
32
18
-
2
3
10
18
25
40
68
62
52
53
74
56
59
(4bit)
DATA IN/OUT
154
151
-
55
56
57
SD03
SDI3
SYNC
WSI
SCKI
14
63
9
10
4
50
30
31
RESET
DSP
DSP48K
DSPON
13
18
27
98
97
79
67
-
9
1
-
SIC
SOC
(8bit)
DATA IN/OUT
LSB
4
12
-
96
91
-
30
35
-
58
21
64
85
80
-
41
46
-
75
68
-
(8bit)
DATA IN/OUT
3
8
1
19
18
2
14
9
12
C GAIN CTL
Y GAIN CTL
C OUT
Y OUT
CAM CLK 4.5M
REF CLK
C PB OUT(4bit)
Y PB OUT(8bit)
C IN(8bit)
LSB
Y IN(8bit)
LSB
V OUT
PROCESS CIRCUIT
FROM/TO
98
97
81
78
96
89
106
99
117
110
----
NV-DS33EG / NV-DS33B / NV-DS33EN / NV-DS33ENA
10
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