UF-8300, UF-8200, UF-7300, UF-7200 (serv.man2) - Panasonic Fax Other Service Manuals (repair manual). Page 7

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UF-7300/7200

UF-8300/8200

1. System CPU

The System CPU (PPC405EP) is a 32-bit RISC (Reduced Instruction Set Computer) type of CPU and
EBC Control (ROM/SRAM), PC133 SDRAM Control, PCI Control, DMA Control, Serial Communication 
Port, Timer, Interrupt Control, Ethernet MAC and IIC Control are integrated into 1 chip. 
The EBC is connected to the Power-on Boot space. The 405 processor will begin with an initial fetch to 
address 0xFFFFFFFC. The EBC is setup to respond to this Boot address and the request will go to 
bank 0. This bank must have a ROM attached with the Boot code to begin the processor execution.

• EBC Control

A peripheral bus control, used to transfer data between the following devices.
Boot ROM (IC22)
Main Program F-ROM (IC19)
System Backup F-ROM (IC18)
API2 (IC11)
MODEM (IC61)
SD Controller (IC42)

• SDRAM Control

Generates High Speed SDRAM Control Signal and Refresh Control when the power is ON.

• PCI Control

A PCI control bus, used to transfer data between the following devices.
Imaging ASIC (ISIS2) (IC17)

• DMA Control

A 4-ch DMA Control, used for memory and UARTs.

• Serial Communication Port (UART)

A 2-ch Serial Communication Port, used to interface the following devices.
CPU: Panel Unit (Panel CPU)
CSS Debug Port for PC

• Timer Control

Used to program the standard timer.

• Interrupt Control

Controls the reception & transfer to CPU the interrupt from ISIS2, Modem, etc.

• Ethernet MAC

Supports Auto-sensing 10Base-T/100Base-TX, full / half duplex modes.

• IIC Control

A 1-ch IIC Port, used to interface the following devices.
SPC PC Board Sub CPU (M16C)
G3B PC Board CPU (SH)