Read Panasonic UF-7000 / UF-8000 / UF-7100 / UF-8100 (serv.man2) Service Manual online
9
SEPT 2005
Ver. 2.0
UF-7100/8100
UF-7000/8000
2.2.
Engine Control PC Board
2.2.1.
IC1 (ASIC)
(A) This block is the Serial Communication Interface with the Engine CPU (IC004).
(B) This block is the Stepping Motor Controller (CH1) to control the 2nd Feeder Motor.
(B) This block is the Stepping Motor Controller (CH1) to control the 2nd Feeder Motor.
(C) This block is the LSU Controller, and it consists of Laser Enable, Power Adjust and Video Data.
2.2.2.
Clock Circuit
The system clock (12.00MHz) is generated by IC002 and X001, and it is supplied to the CPU (IC006) and
IC001.
IC001.
nCS
SCLK
SDI
SD0
SCLK
SDI
SD0
SM1A
nSM1EN
nSM1EN
nLDEN
nADJUST
nVIDEO
nADJUST
nVIDEO
LD5VSW
nRST
nRST
VDD
VSS
GND
nTRST
VSS
GND
nTRST
(A)
(B)
(C)
Chip Select
Serial Clock
Serial Input Data
Serial Output Data
Serial Clock
Serial Input Data
Serial Output Data
Motor Clock
Motor Enable
Laser Enable
Laser Power Adjust
Video Data Output
Laser Power Adjust
Video Data Output
Power Supply Unit Detect
System Reset
System Reset
+5V
CPU (IC006)
I/F
I/F
Stepping Motor
CH1 I/F
CH1 I/F
LSU I/F
IC001 (ASIC)
IC002 (Inverter)
11
10
X001
12.00 MHz
C115
C120
8
R158
C119
22
X0
IC006
(CPU)
R005
9
3
CLK1
IC001
(ASIC)
R159
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