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30
1.2.
Power On Initial Flow Chart
< Check Output : If Signal is not correct, each IC
might be defective >
might be defective >
Initial Flow
Power ON
Hardware Reset
Boot Program in CPU Start
0
Is Cover Open CPU(73) and
BPNT CPU(44) is Low ?
Wait Data from PC
via Parallel I/F
Update Program
Scanning LED Lit &
Scanning LED Flashed
Scanning LED Flashed
CPU I/O Port Set
I/O Device Reset
I/O Device Port Set
System Program(FROM) Start
SDRAM Working Area Clear
PANEL Initial
1
UF-490 (xx)
Below is displayed on LCD
< Check Output : If Signal is not correct, each IC
might be defective >
might be defective >
Power
Matser
Clock
Reset
CNP4.5 3.3V -> IC1 CPU,IC3 SHINE
CNP4.7 5V -> (3)IC4(4)2.5V -> IC3 SHINE
CNP4.7 5V -> (3)IC4(4)2.5V -> IC3 SHINE
5MHz -> (63)CPU(90) 50MHz
-> (103)IC3 SHINE
-> (103)IC3 SHINE
Reset IC2(4) -> -> (32)IC3 SHINE(39)
-> -> (59)IC1 CPU
-> -> (59)IC1 CPU
XTAL
3V
0V
3.3V
0V
CPU (CS0)
IC1 CPU(107) -> -> (26)IC5 FROM
CPU (RD)
IC1 CPU(95) -> -> (28)IC5 FROM
CPU (A1-21)
IC1 CPU(142-118) -> -> (26)IC5 FROM
CPU (D0-D15)
IC1 CPU(114,17-1) -> -> (26)IC5 FROM
nMDMRST
IC1 CPU(84) -> -> (41)IC9 Modem
nFRPRST
IC1 CPU(83) -> -> (44)IC18 FRIP
CPU(PNLTXD)
IC1 CPU(67) -> -> CNP5.5
CPU(PNLRXD)
IC1 CPU(66) -> -> CNP5.6
CPU(PNLRST)
IC1 CPU(85) -> -> CNP5.9
5V
0V
< Check Output : If Signal is not correct, each IC
might be defective >
might be defective >
< Check Output : If Signal is not correct, each IC
might be defective >
might be defective >
...
3.3V
0V
...
N
Y
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