Read Panasonic CY-LXV471F Service Manual online
1
FEATURES
2
2
WIRING CONNECTION (DVD Deck)
2
3
BLOCK DIAGRAM (DVD Servo Block)
3
4
TERMINALS DESCRIPTION
4
5
IC BLOCK DIAGRAM
5
6
DVD PLAYER PARTS LIST
7
7
EXPLODED VIEW (DVD Deck)
11
8
WIRING DIAGRAM
12
9
SCHEMATIC DIAGRAM
15
CONTENTS
Page
Page
1 FEATURES
•
•
•
•
The specifications are based on the main unit
2 WIRING CONNECTION (DVD Deck)
2
3 BLOCK DIAGRAM (DVD Servo Block)
3
4.1. DVD Servo Block
IC301 : MN102H60GAC
Pin
No.
No.
Port
Descriptions
I/O
(V)
(V)
(V)
1
WAITODC
CPU Bus Control
I
3.4
2
NRE
CPU Bus Control
O
0
3
NWEL
CPU Bus Control
O
3.2
4
(NC)
-
-
-
5
XCS0
Flash ROM Chip Select
O
1.4
6
NSRAMCS
SRAM Chip Select
O
2.6
7
NCS
ODC Chip Select
O
3.3
8
NMPEGCS
MPEG Decoder Chip Select
O
3.4
9
NMPEGRST
MPEG Decoder Reset
O
3.4
10
NCSDAC
DAC Chip Select
O
3.4
11
(NC)
-
-
-
12
P57/XWORD
Low Fix
I
0
13
A0
CPU Address Bus
O
0.7
14
A1
CPU Address Bus
O
1.5
15
A2
CPU Address Bus
O
1.7
16
A3
CPU Address Bus
O
1.8
17
33VDD
+3.3V Power Supply
O
3.4
18
(NC)
-
-
-
19
VSS
GND
-
0
20
XI/PS1
Self Test Mode
I
3.3
21
(NC)
-
-
-
22
33VDD
+3.3V Power Supply
-
3.4
23
OSCI
Clock
I
0
24
(NC)
-
-
-
25
MODE
Mode Selector
I
0
26
A4
CPU Address Bus
O
1.6
27
A5
CPU Address Bus
O
2.3
28
A6
CPU Address Bus
O
0.7
29
A7
CPU Address Bus
O
2.6
30
A8
CPU Address Bus
O
0.9
31
A9
CPU Address Bus
O
2.4
32
A10
CPU Address Bus
O
0.7
33
A11
CPU Address Bus
O
2.4
34
33VDD
+3.3V power Supply
-
3.4
35
A12
CPU Address Bus
O
0.9
36
A13
CPU Address Bus
O
0.9
37
A14
CPU Address Bus
O
0.8
38
A15
CPU Address Bus
O
0.6
39
A16
CPU Address Bus
O
0.6
40
A17
CPU Address Bus
O
0
41
A18
Reserve for DVD3.5
CPU Address Bus
CPU Address Bus
O
0.4
42
A19
Reserve for DVD3.6
CPU Address Bus
CPU Address Bus
O
2.4
43
VREFN
(Low Level Fixed)
-
0
44
INNERSW
Inner Switch
I
3.3
45
LOADING
Loading Driver Command Value
O
1.7
46
(NC)
-
-
-
47
-
(Ground pull down)
-
0
48
NGENCS
Serial Bus Chip Select Clock
Generator
Generator
O
3.0
49
NCE2SRAM
SRAM Standby Control
O
3.0
50
CKIO
MPEG DecoderCKIO
O
0
51
SI DATA
Serial Bus SI Data
I
2.9
52
SO DATA
Serial Bus SO Data
O
3.2
53
GENCK
Serial I/F Clock Generator
SCK
SCK
O
3.0
54
VREFP
VREFP
-
3.4
55
STANDBY
Motor Driver Mute
O
3.2
56
GENDATA
Serial I/F Clock Generator SO
O
3.0
57
ODCSEL
ODC IF Select
O
3.3
58
DMUTE
Audio Mute (H: ON, L: OFF)
O
0
59
LODSWON
Photo Enable
O
0
60
LODSW
LOADING SW
I
3.4
61
VSS
GND
-
0
62
P3
Photo SW (H: Close)
I
0
63
P2
Photo SW (H: Close)
I
0
Pin
No.
No.
Port
Descriptions
I/O
(V)
(V)
(V)
64
P1
Photo SW (H: Close)
I
0
65
(NC)
-
-
-
66
33VDD
+3.3V Power Supply
-
3.4
67
S5
DAC Reset Control
O
3.4
68
S3
DAC Chip Select
O
3.4
69
(NC)
-
-
-
70
S0
DAC Data Shist Clock
O
3.4
71
(NC)
-
-
-
72
S1
DAC Serial Data
O
3.4
73
PLL UP0
Pull-up
I
3.3
74
PLL UP1
Pull-up
O
3.3
75
NM1
(High Level Fixed)
-
3.4
76
XIRQ0
Photo SW
O
0
77
XIRO1
FEP reset
O
3.3
78
NINTADSC
ADSC Interrupt
I
3.3
79
XHINT
AV Decoder Interrupt
I
3.3
80
XRQ4
(VDD Pull-Up)
-
3.0
81
ADSEP
(High Level Fixed)
-
3.4
82
RST
System Reset
I
3.3
83
33VDD
+3.3V Power Supply
-
3.4
84
D0
CPU Data Bus
I/O
1.1
85
D1
CPU Data Bus
I/O
0.9
86
D2
CPU Data Bus
I/O
1.4
87
D3
CPU Data Bus
I/O
1.1
88
D4
CPU Data Bus
I/O
1.5
89
D5
CPU Data Bus
I/O
0.9
90
D6
CPU Data Bus
I/O
1.4
91
D7
CPU Data Bus
I/O
1.3
92
VSS
GND
-
0
93
D8
CPU Data Bus
I/O
1.6
94
D9
CPU Data Bus
I/O
1.5
95
D10
CPU Data Bus
I/O
1.8
96
D11
CPU Data Bus
I/O
1.0
97
D12
CPU Data Bus
I/O
1.8
98
D13
CPU Data Bus
I/O
1.8
99
D14
CPU Data Bus
I/O
2.0
100
D15
CPU Data Bus
I/O
1.9
4 TERMINALS DESCRIPTION
4