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A108
A109
A113
A110
A
SCHEMATIC DIAGRAM - 6
DVD MODULE (FPGA) CIRCUIT
DVD MODULE (FPGA) CIRCUIT
SA-PTX7EB/EG
1/2
2/2
TO DVD MODULE (FPGA)
SECTION (2/2)
TO
DIGITAL CIRCUIT
(CN1503)
IN SCHEMATIC - 14
DIGITAL CIRCUIT
(CN1503)
IN SCHEMATIC - 14
B
:+B SIGNAL LINE
: DVD VIDEO SIGNAL LINE
: DIGITAL AUDIO SIGNAL LINE
A
B
C
D
E
F
G
H
1
2
3
4
5
6
7
8
9
10
11
12
13
14
1
2
3
4
5
6
7
8
9
10
11
12
13
14
C3016
0.1
C3015
0.1
J0JJC0000003
LB3001
FL3002
F1J1A1050021
FL3001
F1J1A1050021
J0JJC0000003
LB3003
FL59005
F1J1A1050021
J0JJC0000003
LB3002
C3009
0.1
C3010
0.1
C3008
0.1
C3012
0.1
C3011
0.1
C3006
0.1
C3004
0.1
C3003
0.1
C3005
0.1
C3007
0.1
C3014
0.1
C3013
0.1
R12 VCCO_2(+3.3V)
J9
GND
B5
VCCO_0(+3.3V)
N13 VCCINT(+1.2V)
F1
VCCAUX(+2.5V)
F16
VCCAUX(+2.5V)
A6
VCCAUX(+2.5V)
A11 VCCAUX(+2.5V)
D13 VCCINT
D4
VCCINT
M12 VCCINT(+1.2V)
N4
N4
VCCINT(+1.2V)
E12 VCCINT
E5
VCCINT
M5
VCCINT(+1.2V)
G7
GND
F11
GND
G10
GND
G9
GND
H8
GND
H2
GND
H7
GND
G8
GND
A16
GND
A1
GND
F6
GND
B9
GND
T6
VCCAUX(+2.5V)
T11
VCCAUX(+2.5V)
L1
VCCAUX(+2.5V)
L16
VCCAUX(+2.5V)
J8
GND
H10
GND
H9
GND
J7
GND
E15 VCCO_1(+3.3V)
K7
GND
F10
VCCO_0(+3.3V)
M2
VCCO_3(+3.3V)
M15 VCCO_1(+3.3V)
L7
VCCO_2(+3.3V)
L10
VCCO_2(+3.3V)
R5
VCCO_2(+3.3V)
G11 VCCO_1(+3.3V)
G6
VCCO_3(+3.3V)
K11 VCCO_1(+3.3V)
K6
VCCO_3(+3.3V)
F7
VCCO_0(+3.3V)
K9
GND
L6
GND
T1
GND
R8
GND
T16
GND
L11
GND
K10
GND
K8
GND
B12 VCCO_0(+3.3V)
J10
GND
E2
VCCO_3(+3.3V)
J15
GND
R3012
4.7K
4.7K
4.7K
4.7K
4.7K
4.7K
R3011
4.7K
R3015
R3153
R3014
R3013
LCDD1
LCDD2
LCDD0
22
R3019
100
R3018
R3020
22
SH_SCRRXD1
SH_SCRTXD1
NRST
FPGA_MEM0
R3016
100
100
R3017
SH_SCRCLK1
SH_SCRCE
6.3V47
C3111
R13
VS1
C8
PDOUT
N9
CLK_VCXO_27
P14
VS0
B3
HSWAP
R9
M2
D6
SERI_DATA_SH
D5
CS_SH
F8
FIFO_EMP
M3
XRST
E11
FIFO_FULL
C6
SERI_O_SH
B8
CLK_CPU_SH
L9
M0
T10
M1
T13
VS2
N6
FLD_DBG
H13
SW_DSEL<1>
A7
VS_DBG
E8
VSYNC_DV5
J2
PDOK
B11
FLDFLG_DV5
N8
CLK_VCXO_54
E10
HSYNC_DV5
A10
HBLK_DV5
H16
SW_DSEL<0>
C5
RSTOUT
C7
HS_DBG
H11
DATA_O_R656<1>
M14
DATA_O_R656<0>
P16
DATA_O_R656<3>
M16
DATA_O_R656<2>
F4
TESTO_CLK54
E4
TESTO_CLK27
N3
DUMMY_IN
R3047
LCD_CLK
LCDD15
LCDD13
LCDD11
LCDD10
LCDD8
LCDD6
LCDD4
LCDD5
LCDD7
LCDD9
LCDD12
LCDD14
LRCK
DMIXOUT
SRCK
DV5_ON
LCD_DON
LCDCL1
LCDFLM
22
R3002
22
R3004
22
R3003
SH_SCRTXD1
SH_SCRCE
SH_SCRRXD1
FPGA_MEM0
22
R3176
22
R3175
R3178
22
22
R3177
FPGA_INIT
CONFIG_TX
CONFIG_CLK
FPGA_DONE
PROGRAM
SH_SCRCLK1
NT_PAL_IN
22
R3001
LCDCL2
LB3104
J0JCC0000103
LB3105
J0JCC0000103
6
7
5
9
47
44
39
40
35
31
27
24
21
20
22
16
15
18
17
11
13
12
10
14
19
23
26
25
30
28
29
34
32
33
38
36
37
43
41
42
46
45
49
48
8
1
1
3
4
2
50
50
P3007
LCDD3
G2
TESTOUT1<1>
J5
TESTOUT1<2>
N14
NTSC_PAL_OUT
C13
LCD_DON
G16
DATA_O_R656<6>
J3
TESTOUT1<0>
K16
DATA_O_R656<7>
B6
VSYNC_SH
H1
HSYNC_SH
T2
NTSC_PAL_IN
L2
TESTOUT2<0>
H3
TESTOUT1<6>
H6
TESTOUT1<7>
P2
TESTOUT2<6>
K2
TESTOUT2<5>
K3
TESTOUT2<7>
P1
TESTOUT2<2>
J4
TESTOUT2<1>
R4
TESTOUT2<4>
K1
TESTOUT2<3>
B10
IMG_DATA_SH<5>
E14
IMG_DATA_SH<3>
M13
IMG_DATA_SH<4>
K12
IMG_DATA_SH<11>
D12
IMG_DATA_SH<10>
A13
IMG_DATA_SH<12>
L12
IMG_DATA_SH<7>
L15
IMG_DATA_SH<6>
J13
IMG_DATA_SH<9>
E16
IMG_DATA_SH<8>
H4
TESTOUT1<4>
G3
TESTOUT1<3>
G5
TESTOUT1<5>
C12
IMG_DATA_SH<1>
C9
IMG_DATA_SH<0>
L14
IMG_DATA_SH<2>
NT_PAL_OUT
LCDCL1
LCDFLM
22
R3025
LCDD5
LCDD4
22
R3036
22
R3035
LCDD8
LCDD7
LCDD10
LCDD12
LCDD13
LCDD11
LCDD9
22
R3033
22
R3034
22
R3046
22
R3045
22
R3032
LCDD6
LCDD1
22
R3026
R3043
100
1000P
C3113
LCD_DON
LCDD0
22
R3031
LCDD3
22
R3027
22
R3029
22
R3030
R3028
22
LCDD2
A8
DOT_CLK_SH
L3
DATA_O_R656<5>
LCDCL2
22
R3024
22
R3121
22
R3119
22
R3126
22
R3125
22
R3118
22
R3120
F9
TESTOUT4<5>
A9
TESTOUT4<4>
G4
TESTOUT4<6>
F15
DATAIN_DV5<4>
F12
DATAIN_DV5<6>
G13
DATAIN_DV5<5>
B2
TESTOUT4<0>
B14
TESTOUT4<1>
F14
TESTOUT3<6>
J16
TESTOUT3<5>
T5
TESTOUT3<7>
D10
TESTOUT4<3>
E9
TESTOUT4<2>
G14
DATAIN_DV5<2>
R11
SERI_O_DV5
D8
CLKIN_54
T14
CS_DV5
G15
DATAIN_DV5<1>
J11
DATAIN_DV5<0>
J12
DATAIN_DV5<3>
F13
DATAIN_DV5<7>
22
R3124
22
R3122
22
R3123
D9
TESTOUT4<7>
FPGACS
22
R3117
100
R3042
R_DATA
VCLK
VOUT1
VOUT3
VOUT6
VOUT5
VOUT7
VOUT4
VOUT2
VOUT0
P15
TESTOUT3<3>
M11
CLK_CPU_DV5
N16
TESTOUT3<0>
L13
TESTOUT3<2>
H12
TESTOUT3<1>
C10
IMG_DATA_SH<13>
J14
IMG_DATA_SH<15>
H14
IMG_DATA_SH<14>
N11
SERI_DATA_DV5
K15
TESTOUT3<4>
SBT3
LCDD14
22
R3037
22
R3038
LCDD15
22
R3039
22
R3040
SBO3
100
R3115
100
R3116
22
R3041
D11
DOT_CLK_O_SH
C3001
1000P
K14
DATA_O_R656<4>
LCD_CLK
22
R3022
22
R3023
D+2R5V
NSW1R2V
VOUT1
VOUT0
VOUT6
VOUT5
NRST
VOUT7
VOUT2
VOUT4
VOUT3
DGND
R_DATA
VCLK
SBO3
SBT3
FPGACS
D+3R3V
IC3000
C1ZBZ0003207
FIELD PROGRAMMABLE
DV
DV
DV
DV
DV
DV
DV
DV
DV
DV
DV
DV
DV
DV
DV
DV
DV
DV
DV
DV
DV
DGND
DGND
DGND
NC
SRCK
LRCK
DGND
DGND
DGND
DGND
DGND
DGND
DGND
LCDCLK
LCDD5
LCDD6
LCDD4
LCDD8
LCDD9
LCDD7
LCDD13
LCDD14
LCDD12
LCDD10
LCDD11
LCDD15
PROGRAM
FPGA_DONE
CONFIG_TX
CONFIG_CLK
DV5_ON
DMIXOUT
FPGA_INIT
LCD_CL2
LCD_DON
LCD_CL1
LCD_FLM
NT_PL_IN
SH_SCRCE
SH_SCRCLK
NT_PL_OUT
SH_SCRRXD1
SH_SCRTXD1
CONFIG_RX
FPGA_MEM0
LCDD2
DGND
LCDD0
LCDD1
LCDD3
DA
DV: DVD MODULE (DV5): SCHEMATIC DIAGRAM 1 - 4
HD: DVD MODULE (HDMI): SCHEMATIC DIAGRAM - 5
HD: DVD MODULE (HDMI): SCHEMATIC DIAGRAM - 5
FP: DVD MODULE (FPGA): SCHEMATIC DIAGRAM 6 - 7
DA: DVD MODULE (VIDEO DAC): SCHEMATIC DIAGRAM - 8
DA: DVD MODULE (VIDEO DAC): SCHEMATIC DIAGRAM - 8
GATE ARRAY
IC3000
C1ZBZ0003207
FIELD PROGRAMMABLE
GATE ARRAY
NT_PAL_OUT
R3179
100K
NT_PAL_IN
R3182
470
R3180
1K
SA-PTX7EB / SA-PTX7EG
124
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