Read LG 72LM9500-DA (CHASSIS:LT23J) Service Manual online
System Diagram – Focused on Interface between Analog and Digital Chip
Dual Tuner
+ Demod for CHB
DIF
CVBS(CHB)
SIF
Parallel TS
System
Demux
TS (from GCB)
Audio DSP
Multi-STD
Audio Decoder
BTSC AFE
w/ PLL
1ch L/R
Audio-ADC
24b@48KHz
GBB AFE
1ch@30MHz
w/ PLL
Global Baseband
V/Q, DVB-T/C
CVBS AFE(CHB)
10b@27MHz
CVBS(6ch)
Component(2ch)
3ch Video
AFE
10b@165MHz
w/ LLPLL
PC-RGB
HDMI-Rx 1.4
(1-port PHY)
(1-port PHY)
3D, ARC, 4kx2k
HDMI(1ch)
CVD (CHB)
Capture
Block
(3CH)
(3CH)
AAD
(THAT)
Audio Codec1
(Digital Part)
Mux
Analog Chip
Digital Chip
Audio L/R (5-ch)
SW
I2S(stero)
Sound
DSP
Audio DAC
48KHz
Audio DAC
48KHz
I2S
SPDIF
Video Decoder
(
Dual HD
)
CVBS AFE(2-ch)
12b@54MHz
6+1(clk)+2(gc)
12 : CVBS
Mux
12
Diplay
Engine
MC NR,
Vertical MC IPC
Scaler, PE
OSD, VCR
LVDS
CVBS
Encoder
H.264 Encoder
SD upto 480p
12
Channel
Browser
Browser
PHY
(3-port)
USB2.0
Host (x3)
DDR3-PHY
DDR3(x16) * 3
Ethernet
MAC
MLC NAND
Controller
CPU
Dual C-A9 (1GHz)
Graphic
Engine
2D-VG / 3D Open-ES2.0
Audio
10(data)+1(en)+5(gc)
4(val, err, clk, sop)
+8 (data)
+8 (data)
I2C
I2C
6(gbb, l9da)
I2C
(Headphone)
Line out (main audio)
SCART out
Digital
Audio
Output
LVDS
LVDS
Video
LVDS
Video
OSD
LVDS
Audio PLL
w/ DCO
MIC IN (Mono)
SW
I2S (mono)
3(lrck, lrch, sck)
I2S
I2S
Video DAC
10b@27MHz
CVBS-Out
6 (data)
I2C
SW
SW
CVBS-Out
SW
3D or UD
Data bridge
1 (ARC data)
ARC
(1ch)
I2S or SPDIF
8
Audio Clocks
9
1ch mono
Audio-ADC
24b@48KHz
Audio Codec0
(Digital Part)
Mux
LVDS
interrupt
3(hdmi, 3ch, gbb)
5(gc)
3(lrck, lrch, sck)
3(lrck, lrch, sck)
3(lrck, lrch, sck)
Audio
HDMI
(1-Link)
I2S
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