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60PX950-SA (CHASSIS:PB01B) - LG TV Service Manual (repair manual). Page 95

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Great Company  Great People
Blue Ocean P³ Innovation
20. Block Diagram – 3DF B/D 
(PDP 3DTV)
LVDS (51P
in)
BCM
I2C
L/R DETECT
FPGA RESET
LVDS 2Ch
I2C
L/R DETECT
FPGA RESET
LVDS 2Ch
X-tal
(54MHz)
DDR2
(512Mbitx2) 
PROM
(16Mbit)
2D to 3D
Converter 
(FPGA)
EP3C55F484
3D Formatter
(FPGA)
EP3C55F484
I2C
FPGA RESET
LVDS 2Ch
X-tal
(54MHz)
PROM
(16Mbit)
LVDS 2Ch
(
Left
)
LVDS (80P
in)
LVDS 2Ch
(
Right
)
3D
_S
YN
C
3D_SYNC
■ Input
ƒ 1 LVDS RX (2 channel)
ƒ 10 bit 1920x1080p@60Hz
■ Output
ƒ 2 LVDS TX (4 channel)
ƒ 10 bit 1920x1080p@120Hz 
■ Processing
ƒ 148.5 MHz, 74.24 MHz
ƒ DDR2 IF(153MHz)
ƒ CSC (RGB ÅÆ YUV) included
ƒ Scaler included
ƒ I2C input from LVDS RX
5V_VCC
5V_VCC
3D_SYNC
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