Read LG 50PS2000-ZB (CHASSIS:PD92A) Service Manual online
LVA_1M
A_MDATA[1]
LVB_0P
PCM_OE_N
LVA_1P
A_MADR[9]
PCM_D[0-7]
LVB_CKM
A_MADR[2]
A_MDATA[0]
A_MDATA[2]
A_MADR[0]
A_MDATA[6]
TS_CLK
A_MCLK+
BUF_TS_SYNC
LVA_CKM
A_MADR[7]
LVB_4P
A_BA0
PCM_CE_N
LVA_3M
A_MDATA[7]
A_MDATA[4]
LVB_2P
PCM_IOWR_N
LVA_CKP
LVB_4M
A_MDATA[12]
A_MDATA[8]
A_MADR[8]
PCM_REG_N
A_RAS
A_MADR[11]
A_DQM0
BUF_TS_VAL
T S _ D [ 0 - 7 ]
A_MDATA[14]
LVA_3P
LVB_2M
PCM_IRQA_N
TS_SYNC
A_CAS
A_MADR[10]
A_MADR[3]
LVA_2P
LVB_3P
A_DQM1
A_MCLK-
PCM_RESET
A_MDATA[13]
A_MADR[5]
LVA_4P
A_MADR[4]
LVB_1P
LVB_CKP
A_MDATA[11]
PCM_WAIT_N
A_MADR[6]
A_MDATA[15]
A_MDATA[10]
LVA_2M
A_MDATA[3]
LVB_3M
BUF_TS_DATA[0]
PCM_WE_N
PCM_A[0-14]
A_MADR[1]
LVA_0P
A_BA1
TS_VALID
A_WE
LVB_1M
A_MDATA[5]
BUF_TS_CLK
A_MDATA[9]
PCM_CD_N
A_CLKE
LVA_0M
A_MADR[12]
LVA_4M
LVB_0M
PCM_IORD_N
22
R218
22
R217
22
R214
22
R213
22
R219
22
R220
22
R216
22
R215
A_DQS1M
A_DQS1P
A_DQS0M
A_DQS0P
A_ODT
1/10W
1K
1%
R231
1/10W
1K
1%
R232
B_DQM0
B_MDATA[0]
B_MDATA[2]
B_MADR[12]
B_WE
B_DQS1P
B_MADR[1]
B_MDATA[12]
B_MCLK-
B_MADR[2]
B_BA1
B_MADR[6]
B_MDATA[1]
B_MADR[0]
B_MDATA[7]
B_MADR[5]
B_MDATA[6]
B_MADR[4]
B_ODT
B_MDATA[4]
B_MDATA[15]
B_MDATA[11]
B_MDATA[14]
B_RAS
B_MADR[11]
B_MDATA[9]
B_MDATA[3]
B_MCLK+
B_DQS1M
B_DQM1
B_CAS
B_MADR[7]
B_MADR[10]
B_CLKE
B_DQS0P
B_MDATA[5]
B_DQS0M
B_MADR[8]
B_MADR[9]
B_BA0
B_MDATA[13]
B_MDATA[8]
B_MDATA[10]
B_MADR[3]
1/16W
22
AR200
1/16W
22
AR201
1/16W
22
AR202
1/16W
22
AR203
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
0 . 1 u F
50V
50V
C214
0 . 1 u F
50V
50V
C205
+1.25V_VDDC
+3.3V_AVDD_LPLL
0 . 1 u F
50V
50V
C201
+3.3V_AVDD_MPLL
+1.8V_DDR2_MAIN
0 . 1 u F
50V
50V
C203
+1.25V_AVDD_DVI
0 . 1 u F
50V
50V
C207
0 . 1 u F
50V
50V
C209
+3.3V_AVDD_AU
0 . 1 u F
50V
50V
C206
0 . 1 u F
50V
50V
C213
0 . 1 u F
50V
50V
C210
+3.3V_AVDD_MEMPLL
+3.3V_AVDD_ADC
0 . 1 u F
50V
50V
C208
0 . 1 u F
50V
50V
C200
0 . 1 u F
50V
50V
C215
0 . 1 u F
50V
50V
C204
0 . 1 u F
50V
50V
C216
+3.3V_VDDP
0 . 1 u F
50V
50V
C202
+3.3V_AVDD_VIF
+3.3V_AVDD_OTG
HDMI_CEC
0 . 1 u F
50V
50V
C217
56
R258
56
R229
56
R239
56
R237
56
R259
56
R226
56
R236
56
R247
56
R241
56
R249
56
R225
56
R245
56
R255
56
R228
56
R243
56
R253
56
R257
56
R256
56
R248
56
R252
56
R235
56
R227
56
R244
56
R260
56
R254
56
R246
56
R240
56
R238
56
R242
56
R230
33
R222
33
R223
33
R224
33
R221
100
R212
56
R276
1G
56
R277 1G
A_BA2
B_BA2
33
R234
33
R251
33
R233
33
R250
0
R278
OPT
0
R279
+1.8V_DDR2_MAIN
MSD237HFG(SATURN4 NO-SD HD DIVX)
IC100
GND_1
B15
GND_2
D7
GND_3
D8
GND_4
D12
GND_5
D13
GND_6
F7
GND_7
J 9
GND_8
J 1 0
GND_9
J 1 1
GND_10
J 1 2
GND_11
J 1 3
GND_12
K9
GND_13
K10
GND_14
K11
GND_15
K12
GND_16
K13
GND_17
L9
GND_18
L10
GND_19
L11
GND_20
L12
GND_21
L13
GND_22
L19
GND_23
L20
GND_24
M9
GND_25
M10
GND_26
M11
GND_27
M12
GND_28
M13
GND_29
W6
GND_30
W7
AVDD_AU
P8
AVDD_LPLL
K18
AVDD_MPLL
N7
AVDD_MEMPLL
D14
AVDD_33_1
H7
AVDD_33_2
J 6
AVDD_33_3
J 7
AVDD_33_4
K7
AVDD_USB
F8
AVDD_VIF
P7
AVDD_DM
P13
VDDP_1
N8
VDDP_2
N12
VDDP_3
P11
VDDP_4
P12
AVDD_DDR_1
G11
AVDD_DDR_2
G12
AVDD_DDR_3
G13
AVDD_DDR_4
G14
AVDD_DDR_5
H14
AVDD_DVI
G10
VDDC_1
H9
VDDC_2
H10
VDDC_3
J 1 5
VDDC_4
K15
VDDC_5
L15
VDDC_6
M15
VDDC_7
N10
VDDC_8
N11
VDDC_9
P10
MSD237HFG(SATURN4 NO-SD HD DIVX)
IC100
LVA0M
V20
LVA0P
V19
LVA1M
W20
LVA1P
Y20
LVA2M
Y19
LVA2P
W19
LVACKM
Y18
LVACKP
W18
LVA3M
Y17
LVA3P
W17
LVA4M
Y16
LVA4P
W16
LVB0M
M20
LVB0P
M19
LVB1M
N20
LVB1P
N19
LVB2M
P20
LVB2P
P19
LVBCKM
R20
LVBCKP
R19
LVB3M
T20
LVB3P
T19
LVB4M
U20
LVB4P
U19
TS0DATA[7]
V5
TS0DATA[6]
T8
TS0DATA[5]
T7
TS0DATA[4]
R8
TS0DATA[3]
R7
TS0DATA[2]
U6
TS0DATA[1]
U5
TS0DATA[0]
V4
TS0CLK
Y7
TS0VALID
V6
TS0SYNC
W5
TS1DATA
M17
TS1CLK
N18
TS1VALID
L17
TS1SYNC
P18
PCM_D[7]/CI_D[7]
U7
PCM_D[6]/CI_D[6]
U8
PCM_D[5]/CI_D[5]
U9
PCM_D[4]/CI_D[4]
T9
PCM_D[3]/CI_D[3]
R9
PCM_D[2]/CI_D[2]
P9
PCM_D[1]/CI_D[1]
R10
PCM_D[0]/CI_D[0]
R11
PCM_A[14]/CI_A[14]
V7
PCM_A[13]/CI_A[13]
V8
PCM_A[12]/CI_A[12]
U10
PCM_A[11]/CI_A[11]
T10
PCM_A[10]/CI_A[10]
T11
PCM_A[9]/CI_A[9]
V9
PCM_A[8]/CI_A[8]
U11
PCM_A[7]/CI_A[7]
R12
PCM_A[6]/CI_A[6]
T12
PCM_A[5]/CI_A[5]
U12
PCM_A[4]/CI_A[4]
V12
PCM_A[3]/CI_A[3]
R13
PCM_A[2]/CI_A[2]
T13
PCM_A[1]/CI_A[1]
U13
PCM_A[0]/CI_A[0]
V13
PCMIOR/CI_RD
U18
PCMIOW/CI_WR
T18
PCMREG/CI_CLK
U17
PCMCEN/CI_CS
T17
PCMIRQ/CI_INT
R17
PCMWAIT/CI_WACK
R18
PCMOEN
V18
PCMWEN
V17
CI_RST
P17
CI_CD
N17
A_MVREF
E13
A_DDR2_DQM[1]
A10
A_DDR2_DQM[0]
C9
A_DDR2_DQS[1]
C8
A_DDR2_DQS[0]
B9
A_DDR2_DQSB[1]
B8
A_DDR2_DQSB[0]
A9
A_MDATA[15]
A8
A_MDATA[14]
B10
A_MDATA[13]
A7
A_MDATA[12]
A11
A_MDATA[11]
B11
A_MDATA[10]
B7
A_MDATA[9]
C10
A_MDATA[8]
C7
A_MDATA[7]
C6
A_MDATA[6]
C11
A_MDATA[5]
C5
A_MDATA[4]
C12
A_MDATA[3]
B12
A_MDATA[2]
A6
A_MDATA[1]
A12
A_MDATA[0]
B6
A_MADR[12]
C13
A_MADR[11]
D4
A_MADR[10]
C14
A_MADR[9]
A14
A_MADR[8]
D5
A_MADR[7]
B13
A_MADR[6]
D6
A_MADR[5]
B14
A_MADR[4]
A3
A_MADR[3]
A13
A_MADR[2]
B3
A_MADR[1]
A15
A_MADR[0]
C3
A_BADR[2]
F14
A_BADR[1]
D10
A_BADR[0]
D9
A_MCLK
B5
A_MCLKZ
A5
A_MCLKE
D11
A_ODT
C4
A_WEZ
D3
A_RASZ
B4
A_CASZ
A4
B_MVREF
E15
B_DDR2_DQM[1]
F18
B_DDR2_DQM[0]
E20
B_DDR2_DQS[1]
D20
B_DDR2_DQS[0]
E19
B_DDR2_DQSB[1]
D19
B_DDR2_DQSB[0]
E18
B_MDATA[15]
D18
B_MDATA[14]
F19
B_MDATA[13]
C18
B_MDATA[12]
G18
B_MDATA[11]
G19
B_MDATA[10]
C19
B_MDATA[9]
F20
B_MDATA[8]
C20
B_MDATA[7]
B20
B_MDATA[6]
G20
B_MDATA[5]
A20
B_MDATA[4]
H20
B_MDATA[3]
H19
B_MDATA[2]
B18
B_MDATA[1]
H18
B_MDATA[0]
B19
B_MADR[12]
K20
B_MADR[11]
C15
B_MADR[10]
J 2 0
B_MADR[9]
K19
B_MADR[8]
A16
B_MADR[7]
J 1 7
B_MADR[6]
D15
B_MADR[5]
H17
B_MADR[4]
B16
B_MADR[3]
G17
B_MADR[2]
D16
B_MADR[1]
F17
B_MADR[0]
C16
B_BADR[2]
K17
B_BADR[1]
E17
B_BADR[0]
J 1 9
B_MCLK
A19
B_MCLKZ
A18
B_MCLKE
J 1 8
B_ODT
C17
B_WEZ
D17
B_RASZ
B17
B_CASZ
A17
PCM_A[0]
PCM_A[1]
PCM_A[2]
PCM_A[3]
PCM_A[4]
PCM_A[5]
PCM_A[6]
PCM_A[7]
PCM_A[8]
PCM_A[9]
PCM_A[10]
PCM_A[11]
PCM_A[12]
PCM_D[0]
PCM_A[13]
PCM_D[1]
PCM_A[14]
PCM_D[2]
PCM_D[3]
PCM_D[4]
PCM_D[5]
PCM_D[6]
TS_D[7]
TS_D[6]
TS_D[5]
TS_D[4]
TS_D[3]
TS_D[2]
TS_D[1]
TS_D[0]
PCM_D[7]
2
11
MAIN_2
N e x t R e v i s i o n R e a d y ( S t a n d B y 0 . 2 W ) _ 0 8 0 4 0 3
EAX57566204
N e e d t o s w a p e v e n t o o d d
f o r 1 G M e m o r y
f o r 1 G M e m o r y
2 0 0 9 . 0 4 . 1 5
AIN_2
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