47LX9500-ZA, 47LX950N-ZA, 47LX9800-ZA, 47LX9900-ZA (CHASSIS:LD03R) - LG TV Service Manual (repair manual). Page 53

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THE    SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS 
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE    SYMBOL MARK OF THE SCHEMETIC.
DDR_DQ[28]
DDR_DQ[17]
DDR_DQ[10]
DDR_DQ[0]
SDDR_DQ[20]
DDR_DQ[2]
SDDR_DQ[26]
SDDR_DQ[17]
DDR_DQ[19]
SDDR_DQ[23]
DDR_DQ[9]
DDR_DQ[16]
DDR_DQ[10]
DDR_DQ[29]
DDR_DQ[11]
SDDR_DQ[21]
DDR_DQ[15-0]
DDR_DQ[12]
DDR_DQ[20]
DDR_DQ[30]
DDR_DQ[0]
DDR_DQ[13]
DDR_DQ[15]
DDR_DQ[14]
DDR_DQ[1]
DDR_DQ[15]
DDR_DQ[2]
SDDR_DQ[15]
DDR_DQ[18]
DDR_A[3]
DDR_DQ[21]
DDR_DQ[3]
DDR_A[2]
DDR_DQ[22]
DDR_A[9]
DDR_DQ[4]
SDDR_DQ[25]
SDDR_DQ[18]
DDR_A[8]
DDR_DQ[5]
DDR_A[11]
SDDR_DQ[7]
DDR_DQ[19]
DDR_DQ[3]
DDR_DQ[20]
DDR_DQ[18]
DDR_A[10]
1V8
1V8
DDR_A[2]
DDR_DQ[9]
SDDR_DQ[28]
SDDR_DQ[3]
DDR_A[12-0]
DDR_DQ[31]
SDDR_DQ[9]
SDDR_DQ[30]
DDR_A[12-0]
SDDR_DQ[11]
SDDR_DQ[31]
DDR_DQ[12]
DDR_DQ[23]
DDR_DQ[27]
SDDR_DQ[13]
DDR_DQ[21]
SDDR_DQ[2]
DDR_DQ[24]
DDR_A[1]
DDR_DQ[25]
DDR_DQ[25]
DDR_DQ[13]
DDR_DQ[26]
SDDR_DQ[5]
DDR_DQ[1]
DDR_DQ[27]
DDR_DQ[7]
SDDR_DQ[14]
SDDR_DQ[0]
DDR_A[5]
DDR_A[9]
DDR_A[5]
DDR_DQ[23]
DDR_A[8]
SDDR_DQ[12]
SDDR_DQ[29]
DDR_DQ[5]
DDR_A[1]
DDR_A[11]
DDR_A[12]
DDR_DQ[28]
DDR_A[4]
SDDR_DQ[8]
SDDR_DQ[6]
DDR_A[10]
DDR_A[4]
SDDR_DQ[16]
DDR_A[7]
DDR_DQ[29]
SDDR_DQ[4]
SDDR_DQ[27]
SDDR_DQ[10]
DDR_DQ[17]
DDR_A[12]
DDR_A[6]
DDR_DQ[6]
DDR_DQ[30]
DDR_DQ[14]
DDR_A[0]
DDR_A[3]
DDR_A[7]
DDR_DQ[11]
SDDR_DQ[19]
DDR_DQ[24]
DDR_A[6]
DDR_DQ[4]
DDR_DQ[31-16]
DDR_DQ[8]
DDR_DQ[6]
SDDR_DQ[1]
SDDR_DQ[22]
DDR_DQ[26]
DDR_A[0]
DDR_DQ[31]
DDR_DQ[7]
DDR_DQ[16]
DDR_DQ[22]
SDDR_DQ[24]
DDR_DQ[8]
SDDR_DQ[6]
SDDR_DQ[1]
SDDR_DQ[5]
SDDR_DQ[0]
SDDR_DQ[14]
SDDR_DQ[11]
SDDR_DQ[9]
SDDR_DQ[7]
SDDR_DQ[8]
SDDR_DQ[13]
SDDR_DQ[15]
SDDR_DQ[4]
SDDR_DQ[3]
SDDR_DQ[2]
SDDR_DQ[10]
SDDR_DQ[12]
SDDR_DQ[25]
SDDR_DQ[22]
SDDR_DQ[16]
SDDR_DQ[30]
SDDR_DQ[19]
SDDR_DQ[26]
SDDR_DQ[21]
SDDR_DQ[29]
SDDR_DQ[31]
SDDR_DQ[23]
SDDR_DQ[27]
SDDR_DQ[18]
SDDR_DQ[28]
SDDR_DQ[20]
SDDR_DQ[24]
SDDR_DQ[17]
C1025
0.1uF
16V
C1001
10uF
16V
C1093
0.1uF
16V
C1035
0.1uF
16V
AR1012
56
C1084
0.1uF
16V
AR1016
56
C1098
0.1uF
16V
C1099
0.1uF
16V
C1055
0.1uF
16V
C1046
0.1uF
16V
C2006
0.1uF
16V
C1026
0.1uF
16V
C1059
0.1uF
16V
C1015
0.1uF
16V
C1086
0.1uF
16V
C1091
0.1uF
16V
DDR_VTT
C2000
0.1uF
16V
DDR_A[9]
C1017
0.1uF
16V
C1083
0.1uF
16V
DDR_A[12]
DDR_A[8]
C1081
0.1uF
16V
C1008
0.1uF
16V
C1095
0.1uF
16V
DDR_VTT
C1029
0.1uF
16V
R1012
56
C1056
0.1uF
16V
DDR_A[12]
C1078
0.1uF
16V
DDR2_CKE
DDR_A[2]
C1092
0.1uF
16V
DDR2_ODT
DDR_A[5]
C1022
0.1uF
16V
C1003
0.1uF
16V
C2013
0.1uF
16V
C1097
0.1uF
16V
DDR_A[1]
C1045
0.1uF
16V
C2011
0.1uF
16V
C1065
0.1uF
16V
C1033
0.1uF
16V
C2016
0.1uF
16V
C2009
0.1uF
16V
C1005
0.1uF
16V
DDR_A[6]
DDR_A[10]
C1085
0.1uF
16V
DDR_BA[0]
C1060
0.1uF
16V
C1023
0.1uF
16V
C2004
0.1uF
16V
DDR_A[11]
C1010
0.1uF
16V
C1064
0.1uF
16V
C1058
0.1uF
16V
C1040
0.1uF
16V
C1012
0.1uF
16V
DDR_A[3]
C1094
0.1uF
16V
C1087
0.1uF
16V
C1043
0.1uF
16V
C1048
0.1uF
16V
C2017
0.1uF
16V
C2003
0.1uF
16V
DDR_VTT
C1014
0.1uF
16V
C1079
0.1uF
16V
C1044
0.1uF
16V
C2014
0.1uF
16V
AR1009
56
AR1010
56
C1061
0.1uF
16V
C1054
0.1uF
16V
C2007
0.1uF
16V
DDR_A[4]
C1090
0.1uF
16V
C1007
0.1uF
16V
C1020
0.1uF
16V
C1049
0.1uF
16V
1V2
C2001
0.1uF
16V
DDR_A[7]
C2008
0.1uF
16V
C2002
0.1uF
16V
DDR_A[0]
C2015
0.1uF
16V
DDR_A[11]
DDR2_CKE
/DDR_RAS
C1072
0.1uF
16V
C1096
0.1uF
16V
/DDR_WE
/DDR_WE
1V8
C1024
0.1uF
16V
C1041
0.1uF
16V
C1073
0.1uF
16V
/DDR_CS
C1013
0.1uF
16V
DDR_A[0]
DDR_A[1]
C1032
0.1uF
16V
R1011
56
C2018
0.1uF
16V
C2012
0.1uF
16V
C1037
0.1uF
16V
C1074
0.1uF
16V
AR1014
56
/DDR_RAS
DDR_BA[0]
C1089
0.1uF
16V
2V5
AR1017
56
/DDR_CAS
C1088
0.1uF
16V
1V2
1V8
AR1018
56
C1077
0.1uF
16V
1V8
DDR_A[7]
C1039
0.1uF
16V
DDR_A[5]
C1075
0.1uF
16V
C1036
0.1uF
16V
DDR_BA[1]
C1018
0.1uF
16V
DDR2_ODT
/DDR_CS
C2005
0.1uF
16V
C1082
0.1uF
16V
/DDR_CAS
DDR_A[6]
C1051
0.1uF
16V
AR1011
56
DDR_A[3]
DDR_A[9]
AR1013
56
DDR_A[10]
DDR_A[8]
C1062
0.1uF
16V
C1063
0.1uF
16V
C1002
0.1uF
16V
C2010
0.1uF
16V
C1016
0.1uF
16V
C1080
0.1uF
16V
DDR_A[4]
AR1015
56
DDR_BA[1]
2V5
C1052
0.1uF
16V
C1057
0.1uF
16V
C1021
0.1uF
16V
DDR_A[2]
C1076
0.1uF
16V
C1038
0.1uF
16V
C1034
0.1uF
16V
C1050
0.1uF
16V
C1053
100pF
50V
C1047
10uF
16V
1V2
C1070
10uF
16V
C1067
100pF
50V
C1071
10uF
16V
C1066
100pF
50V
1V8
2V5
C1068
0.1uF
16V
C1069
0.1uF
16V
2V5
DDR_A[0]
FPGA_VSYNC_1V8
DDR_A[8]
/DDR_CAS
DDR_A[2]
DDR_LDQS[0]
DDR2_CLK
/DDR2_CLK
/DDR_RAS
DDR_LDM[0]
DDR_UDQS[0]
DDR_A[9]
DDR_A[1]
DDR_A[4]
DDR_A[11]
DDR_A[6]
/DDR_CS
DDR_A[5]
DDR2_ODT
C1011
470pF
50V
C1009
0.1uF
16V
DDR_VREF0
DDR_BA[0]
DDR_BA[1]
/DDR_WE
DDR_A[12]
DDR_UDQS[1]
DDR_A[10]
DDR_LDQS[1]
DDR_A[3]
DDR_A[7]
DDR_LDM[1]
DDR2_CKE
DDR_UDM[0]
DDR_UDM[1]
C1027
0.1uF
16V
C1030
470pF
50V
DDR_VREF1
/DDR_CAS
DDR_BA[1]
DDR_UDM[1]
/DDR_CAS
C1019
100pF
50V
IC1002
H5PS5162FFR-S6C
J2
VREF
J8
CK
H2
VSSQ2
B7
UDQS
N8
A4
P8
A8
L1
NC4
L2
BA0
R8
NC3
K7
RAS
F8
VSSQ3
F3
LDM
P3
A9
M3
A1
N3
A5
K8
CK
R3
NC5
L3
BA1
J7
VSSDL
L7
CAS
F2
VSSQ4
B3
UDM
M2
A10/AP
K2
CKE
R7
NC6
M7
A2
N7
A6
M8
A0
J1
VDDL
K3
WE
E8
LDQS
P7
A11
K9
ODT
A2
NC1
N2
A3
P2
A7
H8
VSSQ1
F7
LDQS
A8
UDQS
R2
A12
L8
CS
E2
NC2
E7
VSSQ5
D8
VSSQ6
D2
VSSQ7
A7
VSSQ8
B8
VSSQ9
B2
VSSQ10
P9
VSS1
N1
VSS2
J3
VSS3
E3
VSS4
A3
VSS5
G9
VDDQ1
G7
VDDQ2
G3
VDDQ3
G1
VDDQ4
E9
VDDQ5
C9
VDDQ6
C7
VDDQ7
C3
VDDQ8
C1
VDDQ9
A9
VDDQ10
R1
VDD1
M9
VDD2
J9
VDD3
E1
VDD4
A1
VDD5
B9
DQ15
B1
DQ14
D9
DQ13
D1
DQ12
D3
DQ11
D7
DQ10
C2
DQ9
C8
DQ8
F9
DQ7
F1
DQ6
H9
DQ5
H1
DQ4
H3
DQ3
H7
DQ2
G2
DQ1
G8
DQ0
1V8
C1042
100pF
50V
C1028
0.1uF
16V
DDR2_CLK
/DDR_CS
DDR_LDM[0]
SDDR_DQ[31-16]
R1002 33
SDDR_DQ[15-0]
R1001
100
DDR_BA[0]
/DDR_RAS
DDR_A[12-0]
DDR_A[12-0]
AR1008
33
R1003 33
DDR_LDQS[1]
C1031
470pF
50V
DDR_LDM[1]
AR1005
33
DDR2_CKE
IC1001
H5PS5162FFR-S6C
J2
VREF
J8
CK
H2
VSSQ2
B7
UDQS
N8
A4
P8
A8
L1
NC4
L2
BA0
R8
NC3
K7
RAS
F8
VSSQ3
F3
LDM
P3
A9
M3
A1
N3
A5
K8
CK
R3
NC5
L3
BA1
J7
VSSDL
L7
CAS
F2
VSSQ4
B3
UDM
M2
A10/AP
K2
CKE
R7
NC6
M7
A2
N7
A6
M8
A0
J1
VDDL
K3
WE
E8
LDQS
P7
A11
K9
ODT
A2
NC1
N2
A3
P2
A7
H8
VSSQ1
F7
LDQS
A8
UDQS
R2
A12
L8
CS
E2
NC2
E7
VSSQ5
D8
VSSQ6
D2
VSSQ7
A7
VSSQ8
B8
VSSQ9
B2
VSSQ10
P9
VSS1
N1
VSS2
J3
VSS3
E3
VSS4
A3
VSS5
G9
VDDQ1
G7
VDDQ2
G3
VDDQ3
G1
VDDQ4
E9
VDDQ5
C9
VDDQ6
C7
VDDQ7
C3
VDDQ8
C1
VDDQ9
A9
VDDQ10
R1
VDD1
M9
VDD2
J9
VDD3
E1
VDD4
A1
VDD5
B9
DQ15
B1
DQ14
D9
DQ13
D1
DQ12
D3
DQ11
D7
DQ10
C2
DQ9
C8
DQ8
F9
DQ7
F1
DQ6
H9
DQ5
H1
DQ4
H3
DQ3
H7
DQ2
G2
DQ1
G8
DQ0
DDR_BA[1]
1V8
DDR2_ODT
DDR_VREF1
DDR2_CLK
AR1004
33
/DDR_RAS
/DDR_CS
AR1007
33
R1005 1K
DDR_BA[0]
DDR2_CKE
DDR_UDQS[1]
/DDR_WE
/DDR2_CLK
R1007 33
R1009 1K
R1006
100
R1010 1K
/DDR2_CLK
AR1001
33
DDR_LDQS[0]
DDR_UDM[0]
AR1006
33
DDR_UDQS[0]
DDR2_ODT
/DDR_WE
R1008 33
R1004 1K
DDR_VREF0
C1006
470pF
50V
AR1003
33
AR1002
33
C1004
0.1uF
16V
SDDR_DQ[15-0]
SDDR_DQ[31-16]
FRAME_INFO_1V8
Q1002
2SC3052
E
B
C
R1013
10K
R1015
10K
Q1001
2SC3052
E
B
C
R1014
10K
R1017
22
+3.3V
3D_FRAME_INFO
FRAME_INFO_1V8
R1022
22
R1020
10K
R1019
10K
+3.3V
Q1003
2SC3052
E
B
C
Q1004
2SC3052
E
B
C
R1018
10K
FPGA_VSYNC_1V8
FPGA_VSYNC
1V8
+3.3V
R1016
3.3K
R1025
10K
R1027
22
R1023
10K
OPT
1V8
Q1005
2SC3052
E
B
C
Q1006
2SC3052
E
B
C
L/R_SYNC
R1026
3.3K
+3.3V
L/R_SYNC_1V8
R1024
10K
L/R_SYNC_1V8
R1021
1K
IC1000
EP3C55F484C6N
J11
VCCINT[0]
J12
VCCINT[1]
L14
VCCINT[2]
M14
VCCINT[3]
P11
VCCINT[4]
P12
VCCINT[5]
L9
VCCINT[6]
M9
VCCINT[7]
J13
VCCINT[8]
J14
VCCINT[9]
K14
VCCINT[10]
J10
VCCINT[11]
K9
VCCINT[12]
N9
VCCINT[13]
P9
VCCINT[14]
P10
VCCINT[15]
P13
VCCINT[16]
P14
VCCINT[17]
N14
VCCINT[18]
J16
VCCINT[19]
K15
VCCINT[20]
L16
VCCINT[21]
M15
VCCINT[22]
R12
VCCINT[23]
R10
VCCINT[24]
R8
VCCINT[25]
H9
VCCINT[26]
G12
VCCINT[27]
J8
VCCINT[28]
M8
VCCINT[29]
T7
VCCINT[30]
T9
VCCINT[31]
T13
VCCINT[32]
P15
VCCINT[33]
H15
VCCINT[34]
H11
VCCINT[35]
K8
VCCINT[36]
L7
VCCINT[37]
D4
VCCIO1[0]
F4
VCCIO1[1]
K4
VCCIO1[2]
N4
VCCIO2[0]
U4
VCCIO2[1]
W4
VCCIO2[2]
AB2
VCCIO3[0]
W5
VCCIO3[1]
W9
VCCIO3[2]
W11
VCCIO3[3]
AB21
VCCIO4[0]
W12
VCCIO4[1]
W16
VCCIO4[2]
W18
VCCIO4[3]
P18
VCCIO5[0]
V19
VCCIO5[1]
Y19
VCCIO5[2]
E19
VCCIO6[0]
G19
VCCIO6[1]
L19
VCCIO6[2]
A21
VCCIO7[0]
D12
VCCIO7[1]
D14
VCCIO7[2]
D16
VCCIO7[3]
A2
VCCIO8[0]
D5
VCCIO8[1]
D9
VCCIO8[2]
D11
VCCIO8[3]
IC1000
EP3C55F484C6N
L10
GND[0]
L11
GND[1]
M10
GND[2]
M11
GND[3]
L12
GND[4]
L13
GND[5]
M12
GND[6]
M13
GND[7]
N11
GND[8]
K11
GND[9]
N12
GND[10]
K12
GND[11]
K13
GND[12]
N13
GND[13]
N10
GND[14]
K10
GND[15]
J9
GND[16]
F12
GND[17]
H12
GND[18]
H13
GND[19]
J15
GND[20]
K16
GND[21]
L15
GND[22]
N15
GND[23]
R13
GND[24]
R11
GND[25]
R9
GND[26]
P8
GND[27]
H14
GND[28]
H10
GND[29]
H8
GND[30]
N8
GND[31]
R7
GND[32]
T8
GND[33]
T12
GND[34]
P16
GND[35]
L8
GND[36]
M7
GND[37]
A1
GND[38]
C5
GND[39]
C9
GND[40]
C11
GND[41]
C12
GND[42]
C14
GND[43]
C16
GND[44]
A22
GND[45]
E20
GND[46]
G20
GND[47]
L20
GND[48]
P19
GND[49]
V20
GND[50]
Y20
GND[51]
AB22
GND[52]
Y18
GND[53]
Y16
GND[54]
Y12
GND[55]
Y11
GND[56]
Y9
GND[57]
Y5
GND[58]
AB1
GND[59]
N3
GND[60]
U3
GND[61]
W3
GND[62]
D3
GND[63]
F3
GND[64]
K3
GND[65]
IC1000
EP3C55F484C6N
AA12
CLK13
AB12
CLK12
AA13
B4_IO[0]
AB13
B4_IO[1]
AA14
B4_IO[2]
AB14
B4_IO[3]
V12
B4_IO[4]
W13
B4_IO[5]
Y13
B4_IO[6]
AA15
B4_IO[7]
AB15
B4_IO[8]
U12
B4_IO[9]
Y14
B4_IO[10]
Y15
B4_IO[11]
AA16
B4_IO[12]
AB16
B4_IO[13]
V13
B4_IO[14]
W14
B4_IO[15]
U13
B4_IO[16]
V14
B4_IO[17]
U14
B4_IO[18]
U15
B4_IO[19]
V15
B4_IO[20]
W15
B4_IO[21]
T14
B4_IO[22]
T15
B4_IO[23]
AB18
B4_IO[24]
AA17
B4_IO[25]
AB17
B4_IO[26]
AA18
B4_IO[27]
AA19
B4_IO[28]
AB19
B4_IO[29]
W17
B4_IO[30]
Y17
B4_IO[31]
AA20
B4_IO[32]
AB20
B4_IO[33]
V16
B4_IO[34]
U16
B4_IO[35]
U17
B4_IO[36]
T16
B4_IO[37]
R16
B4_IO[38]
R14
B4_IO[39]
R15
B4_IO[40]
IC1000
EP3C55F484C6N
V6
B3_IO[0]
V5
B3_IO[1]
U7
B3_IO[2]
U8
B3_IO[3]
Y4
B3_IO[4]
Y3
B3_IO[5]
Y6
B3_IO[6]
AA3
B3_IO[7]
AB3
B3_IO[8]
W6
B3_IO[9]
V7
B3_IO[10]
AA4
B3_IO[11]
AB4
B3_IO[12]
AA5
B3_IO[13]
AA6
B3_IO[14]
AB6
B3_IO[15]
AB5
B3_IO[16]
W7
B3_IO[17]
Y7
B3_IO[18]
U9
B3_IO[19]
V8
B3_IO[20]
W8
B3_IO[21]
AA7
B3_IO[22]
AB7
B3_IO[23]
Y8
B3_IO[24]
T10
B3_IO[25]
T11
B3_IO[26]
V9
B3_IO[27]
V10
B3_IO[28]
U10
B3_IO[29]
AA8
B3_IO[30]
AB8
B3_IO[31]
AA9
B3_IO[32]
AB9
B3_IO[33]
U11
B3_IO[34]
V11
B3_IO[35]
W10
B3_IO[36]
Y10
B3_IO[37]
AA10
B3_IO[38]
AB10
B3_IO[39]
AA11
CLK15
AB11
CLK14
R1028
10K
L/R_SYNC_FRC_OUT
+3.3V
LVDS_STABLE_1V8
1V8
R1029
10K
OPT
FPGA_D/L_CTRL
Q1008
2SC3052
OPT
E
B
C
R1030
10K
OPT
R1032
3.3K
OPT
Q1007
2SC3052
OPT
E
B
C
R1033
22
OPT
R1031
10K
OPT
LVDS_STABLE_1V8
3D_DIMMING_1V8
+3.3V
3D_DIMMING_1V8
R1034
10K
R1038
22
R1037
1K
R1036
10K
Q1010
2SC3052
E
B
C
+3.3V
R1035
10K
3D_DIMMING
Q1009
2SC3052
E
B
C
R1042
1K
R1043
22
R1039
10K
Q1011
2SC3052
E
B
C
R1040
10K
R1041
10K
3D_DIMMING_2_1V8
+3.3V
+3.3V
3D_DIMMING_2
Q1012
2SC3052
E
B
C
3D_DIMMING_2_1V8
3D + 240 FRC + TCON BOARD
10
DDR2
10
2009. 11. 13
3D Frame Info Level Shift (3.3V to 1.8V)
FPGA V-SYNC Level Shift (1.8V to 3.3V)
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