Read LG 47LX9500-SA (CHASSIS:LJ03R) Service Manual online
2
2. 3D Formatter B/D
LG1120 (FRC)
S-Flash
(2MBIT)
DDR2 * 4
(512MBIT)
HW option
Dual Display
Control with
240Hz
(FRC)
TL2425MC(T-CON)
TL2425MC(T-CON)
LVDS_TX4(DATA[10]+CLK[2]
LVDS_TX3(DATA[10]+CLK[2]
LVDS_TX2(DATA[10]+CLK[2]
LVDS_TX1(DATA[10]+CLK[2]
LVDS_TX8(DATA[10]+CLK[2]
LVDS_TX7(DATA[10]+CLK[2]
LVDS_TX6(DATA[10]+CLK[2]
LVDS_TX5(DATA[10]+CLK[2]
(960 X 1080 @ 240Hz)
(960 X 1080 @ 240Hz)
EEPROM
EEPROM
To panel
Left mini-LVDS signals (data[12]+clk[2]
Right mini-LVDS signals (data[12]+clk[2]
Left mini-LVDS signals (data[12]+clk[2]
Right mini-LVDS signals (data[12]+clk[2]
(960 X 1080 @ 240Hz)
(960 X 1080 @ 240Hz)
FPGA
(EP3C55F484C6N)
DDR2 * 2
(512MBIT)
S-Flash
EPCS16SI8N
(2MBIT)
LVDS_TX4(DATA[10]+CLK[2]
LVDS_TX3(DATA[10]+CLK[2]
LVDS_TX2(DATA[10]+CLK[2]
LVDS_TX1(DATA[10]+CLK[2]
LVDS_TX8(DATA[10]+CLK[2]
LVDS_TX7(DATA[10]+CLK[2]
LVDS_TX6(DATA[10]+CLK[2]
LVDS_TX5(DATA[10]+CLK[2]
(960 X 1080 @ 240Hz)
(960 X 1080 @ 240Hz)
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