Read LG 47LD950C (CHASSIS:LA92Y) Service Manual online
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
ASDO
DATA0
/CSO
/CONFIG
/STATUS
DCLK
/CE
CONFIG_DONE
2V5
R134
1K
1K
L101
BLM18PG121SN1D
X100
54.0000MHz
4
VDD
1
TRISTATE/OPEN
2
GND
3
OUTPUT
DCLK
R119
22
22
SYSCLK
2V5
R121
22
22
/STATUS
C116
10uF
16V
10uF
16V
R120
27
27
R131
10K
10K
/CE
R133
10K
10K
ASDO
IC101
EPCS16SI8N_
3
VCC
2
DATA
4
GND
1
NCS
5
ASDI
6
DCLK
7
VCC_1
8
VCC_2
C118
100pF
50V
100pF
50V
R132
10K
10K
2V5
C121
0.1uF
16V
0.1uF
16V
R130
10K
C117
0.1uF
16V
0.1uF
16V
R122
22
22
/CONFIG
R117
22
22
/CSO
C119
10pF
10pF
DATA0
RD2+
RA1+
RB2-
RE2-
RC2-
RA2-
RA1-
RC2+
RA2+
RB2+
RE2+
RD2-
RE1+
RE3+
RB4-
RD3-
RCLK1+
RA4+
RE4-
RE4+
RD4+
RC4+
RD1-
RA3+
RE3-
RB1+
RA4-
RD4-
RC4-
RA3-
RCLK4-
RB4+
RCLK4+
RB3+
RC1+
RB1-
RC3+
RE1-
RCLK1-
RB3-
RD3+
RC3-
RD1+
RC1-
P100
TF05-51S
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
OPC_OUT1
SDA
R159
100
R155
100
RCLK2+
C104
10pF
50V
10pF
50V
READY
C105
10pF
50V
10pF
50V
READY
RE2-
R104
22
R108
22
RB1-
R105
22
RD1+
R167
100
C108
100pF
50V
100pF
50V
R165
100
RA2+
RCLK2-
R158
100
R156
100
BIT_SELECT
PWM_DIM
RC1+
RD1-
RB2-
/3D_FPGA_RESET
C106
10uF
16V
10uF
16V
SCL
3V3
R161
22
22
R107
22
R102
22
RD2+
R164
100
C107
0.1uF
50V
0.1uF
50V
12V_TCON
RA1+
R109
22
RC1-
RE1+
R157
100
OPC_OUT2
OPC_ENABLE
R162
100
R160
100
RD2-
RA1-
RC2+
RCLK1+
RE1-
R103
0
R100
4.7K
READY
R163
100
LVDS_SELECT
R106
22
R110
22
RA2-
RC2-
3D_POWER_EN
R166
100
RE2+
R101
4.7K
READY
RB1+
RB2+
RCLK1-
RCLK3+
R175
100
R179
100
RC4-
RE3+
R174
100
RB3-
P101
TF05-41S
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
R178
100
RD4-
+12V_FORMATTER
RB4+
R173
100
RCLK3-
R177
100
RA3+
C111
100pF
50V
100pF
50V
RCLK4+
RE3-
R172
100
RC3+
C109
10uF
16V
10uF
16V
RE4+
RB4-
R171
100
RD3+
RA3-
C110
0.1uF
50V
0.1uF
50V
RCLK4-
R170
100
RA4+
RC3-
RE4-
RC4+
R169
100
RD3-
R176
100
RB3+
RD4+
R168
100
RA4-
TDI
TDO
TCK
TMS
C120
0.1uF
16V
R123
22
R126
22
2V5
R125
22
R128
1K
R124
1K
R127
1K
P104
YFDW254-10S
1
2
3
4
5
6
7
8
9
10
R129
22
TDO
TDI
TMS
TCK
SYSCLK
CONFIG_DONE
MSEL[3]
MSEL[2]
MSEL[0]
/RESET2V5
MSEL[1]
R141
0
READY
R135
0
READY
MSEL[1]
R136
0
READY
R139
1K
MSEL[0]
MSEL[3]
R140
1K
R137
4.7K
AR100
22
2V5
MSEL[2]
TC1+
TA2-
TD1+
TB1+
TCLK1+
TD1-
TB1-
TA1+
TA1-
TA4+
TE2-
TB2-
TD2+
TB3+
TC1-
TCLK4-
TA3-
TC3-
TB2+
TE4+
TE3+
TD4+
TA3+
TCLK3+
TD2-
TE1+
TCLK2-
TCLK3-
TD3+
TE3-
TA2+
TE4-
TE2+
TA4-
TCLK4+
SDA2V5
TCLK2+
TB3-
TB4-
TC4-
TD3-
TCLK1-
TE1-
TB4+
TC4+
SCL2V5
TC2+
TC2-
TD4-
R150
22
22
OPT
D101
SAM2333
OPT
A2[RD]
C
A1[GN]
TP[3]
TA4+
TA3+
TD1+
TC1-
TA4-
C112
22uF
22uF
R154
22
22
OPT
TA3-
TB3-
TCLK2+
P102
TF05-51S
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
TP[5]
TCLK1+
BIT_SELECT
TE1-
TA2-
R118
0
READY
TP[1]
TP[4]
TD2+
R115
22
D100
SAM2333
OPT
A2[RD]
C
A1[GN]
D102
SAM2333
OPT
A2[RD]
C
A1[GN]
TC4-
R114
22
TC2+
TA2+
OPC_OUT2
TE2-
OPC_ENABLE
C114
0.1uF
50V
0.1uF
50V
TE2+
L100
CB3216PA501E
TCLK4+
R153
1K
1K
OPT
LVDS_SELECT
R145
1K
1K
OPT
TC4+
D103
SAM2333
OPT
A2[RD]
C
A1[GN]
R113
22
PWM_DIM
TCLK3-
TP[2]
TCLK2-
TD2-
R116
22
P103
TF05-41S
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
TC1+
D105
SAM2333
OPT
A2[RD]
C
A1[GN]
TD3-
TE4-
TP[0]
TE4+
TB1-
TCLK4-
TB4+
TB2-
TA1-
TD4-
R111
22
TCLK1-
C113
10uF
16V
10uF
16V
R144
22
22
OPT
R149
1K
1K
OPT
TC3+
12V_TCON
R143
1K
1K
OPT
D104
SAM2333
OPT
A2[RD]
C
A1[GN]
R151
1K
1K
OPT
R180
0
READY
TA1+
R112
22
TC2-
R146
22
22
OPT
R148
22
22
OPT
TB4-
TC3-
TD1-
TB2+
TE3-
TD4+
OPC_OUT1
R147
1K
1K
OPT
TE3+
TE1+
TB3+
TCLK3+
C115
100pF
50V
100pF
50V
TD3+
R152
22
22
OPT
TB1+
TP[1]
TP[3]
TP[5]
TP[0]
TP[2]
TP[4]
IC100
EP3C55F484C8N
RXA0
N2
RXA0(N)
N1
RXA1
P2
RXA1(N)
P1
RXA2
R2
RXA2(N)
R1
RXA3
U2
RXA3(N)
U1
RXA4
V2
RXA4(N)
V1
RXACLK
T2
RXACLK(N)
T1
RXB0
B2
RXB0(N)
B1
RXB1
C2
RXB1(N)
C1
RXB2
F2
RXB2(N)
F1
RXB3
H2
RXB3(N)
H1
RXB4
J2
RXB4(N)
J1
RXBCLK
G2
RXBCLK(N)
G1
IC100
EP3C55F484C8N
NSTATUS
K6
NCONFIG
K5
CONFIG_DONE
M18
DCLK
K2
TCK
L2
TDO
L4
TMS
L1
TDI
L5
DATA0
K1
MSEL0
M17
MSEL1
L18
MSEL2
L17
MSEL3
K20
NCE
L3
ASDO
D1
NCSO
E2
SYSCLK54
G21
RST_N
G22
SCL
A3
SDA
B3
TEST7
J21
TEST6
J20
TEST5
J19
TEST4
J18
TEST3
H21
TEST2
H20
TEST1
H19
TEST0
H18
LED3
E21
LED2
E22
LED1
F19
LED0
F20
IC100
EP3C55F484C8N
NC_1
A11
NC_2
A12
NC_3
A20
NC_4
AA1
NC_5
AA2
NC_6
AA11
NC_7
AA12
NC_8
AA20
NC_9
AB5
NC_10
AB6
NC_11
AB11
NC_12
AB12
NC_13
B4
NC_14
B11
NC_15
B12
NC_16
B21
NC_17
B22
NC_18
C3
NC_19
C4
NC_20
C10
NC_21
C15
NC_22
C20
NC_23
C21
NC_24
C22
NC_25
D2
NC_26
D6
NC_27
D17
NC_28
D20
NC_29
D21
NC_30
D22
NC_31
E1
NC_32
E3
NC_33
E4
NC_34
E5
NC_35
E6
NC_36
E7
NC_37
E8
NC_38
E9
NC_39
E11
NC_40
E12
NC_41
E13
NC_42
E14
NC_43
E15
NC_44
F7
NC_45
F8
NC_46
F9
NC_47
F10
NC_48
F11
NC_49
F13
NC_50
F14
NC_51
F15
NC_52
F16
NC_53
F17
NC_54
F21
NC_55
F22
NC_56
G3
NC_57
G4
NC_58
G5
NC_59
G7
NC_60
G8
NC_61
G9
NC_62
G10
NC_63
G11
NC_64
G13
NC_65
G14
NC_66
G15
NC_67
G16
NC_68
G17
NC_69
G18
NC_70
H3
NC_71
H4
NC_72
H5
NC_73
H6
NC_74
H7
NC_75
H16
NC_76
H17
NC_77
J3
NC_78
J4
NC_79
J5
NC_80
J6
NC_81
J7
NC_82
J17
NC_83
K7
NC_84
K19
NC_85
L6
NC_86
M1
NC_87
M2
NC_88
M3
NC_89
M4
NC_90
M5
NC_91
M6
NC_92
N5
NC_93
N6
NC_94
N7
NC_95
N16
NC_96
N17
NC_97
P3
NC_98
P4
NC_99
P5
NC_100
P6
NC_101
P7
NC_102
P20
NC_103
R3
NC_104
R4
NC_105
R5
NC_106
R6
NC_107
R15
NC_108
T3
NC_109
T4
NC_110
T5
NC_111
T10
NC_112
T11
NC_113
T14
NC_114
T21
NC_115
T22
NC_116
U7
NC_117
U8
NC_118
U13
NC_119
U19
NC_120
V3
NC_121
V4
NC_122
V6
NC_123
V7
NC_124
W1
NC_125
W2
NC_126
Y1
NC_127
Y2
IC100
EP3C55F484C8N
LVDS_OUT_R1[9]
D13
LVDS_OUT_R1[8]
A10
LVDS_OUT_R1[7]
B10
LVDS_OUT_R1[6]
D10
LVDS_OUT_R1[5]
E10
LVDS_OUT_R1[4]
A9
LVDS_OUT_R1[3]
B9
LVDS_OUT_R1[2]
A8
LVDS_OUT_R1[1]
B8
LVDS_OUT_R1[0]
C8
LVDS_OUT_G1[9]
A16
LVDS_OUT_G1[8]
B16
LVDS_OUT_G1[7]
A15
LVDS_OUT_G1[6]
B15
LVDS_OUT_G1[5]
D15
LVDS_OUT_G1[4]
A14
LVDS_OUT_G1[3]
B14
LVDS_OUT_G1[2]
A13
LVDS_OUT_G1[1]
B13
LVDS_OUT_G1[0]
C13
LVDS_OUT_B1[9]
C19
LVDS_OUT_B1[8]
D19
LVDS_OUT_B1[7]
A18
LVDS_OUT_B1[6]
B18
LVDS_OUT_B1[5]
C18
LVDS_OUT_B1[4]
D18
LVDS_OUT_B1[3]
A17
LVDS_OUT_B1[2]
B17
LVDS_OUT_B1[1]
C17
LVDS_OUT_B1[0]
E16
LVDS_OUT_PIXCLK1
A4
LVDS_OUT_DE1
B20
LVDS_OUT_HS1
A19
LVDS_OUT_VS1
B19
GPIO_0
D8
GPIO_1
A7
GPIO_2
B7
GPIO_3
C7
GPIO_4
D7
GPIO_5
A6
GPIO_6
B6
GPIO_7
C6
GPIO_8
A5
GPIO_9
B5
LVDS_OUT_R2[9]
M20
LVDS_OUT_R2[8]
M21
LVDS_OUT_R2[7]
M22
LVDS_OUT_R2[6]
L21
LVDS_OUT_R2[5]
L22
LVDS_OUT_R2[4]
K17
LVDS_OUT_R2[3]
K18
LVDS_OUT_R2[2]
K21
LVDS_OUT_R2[1]
K22
LVDS_OUT_R2[0]
J22
LVDS_OUT_G2[9]
P17
LVDS_OUT_G2[8]
P21
LVDS_OUT_G2[7]
P22
LVDS_OUT_G2[6]
N18
LVDS_OUT_G2[5]
N19
LVDS_OUT_G2[4]
N20
LVDS_OUT_G2[3]
N21
LVDS_OUT_G2[2]
N22
LVDS_OUT_G2[1]
M16
LVDS_OUT_G2[0]
M19
LVDS_OUT_B2[9]
T17
LVDS_OUT_B2[8]
T18
LVDS_OUT_B2[7]
T19
LVDS_OUT_B2[6]
T20
LVDS_OUT_B2[5]
R17
LVDS_OUT_B2[4]
R18
LVDS_OUT_B2[3]
R19
LVDS_OUT_B2[2]
R20
LVDS_OUT_B2[1]
R21
LVDS_OUT_B2[0]
R22
LVDS_OUT_PIXCLK2
H22
LVDS_OUT_DE2
U20
LVDS_OUT_HS2
U22
LVDS_OUT_VS2
U21
GPIO_10
V21
GPIO_11
V22
GPIO_12
AA21
GPIO_13
W21
GPIO_14
W22
GPIO_15
AA22
GPIO_16
W20
GPIO_17
Y21
GPIO_18
W19
GPIO_19
Y22
TC3+
RCLK3+
RCLK3-
RCLK2-
RCLK2+
R138
4.7K
R142
0
READY
LVDS
2009/10/22
1 4
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