Read LG 42PB4DTH-UB / CHASIS / PA72A Service Manual online
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DIAGRAMA EN BLOQUE & GUÍA PARA SOLUCIONES DE PROBLEMAS
MUX
CPLD
LGDT3502
POD/OOB
Controller
Video In/Out
Video In/Out
Side AV_2
V,LR
3
Rear AV_1
V, LR
3
Rear S_1
YC
2
Side S_2
YC
2
MNT_V_Out
M_MSP
4440
AV_L/R_OUT
LR
2
IN1
OUT2
OUT1
OUT1
TV
IN4
IN1
IN4
IN5
OUT3
RGB-PC
5
RGBHV
Comp_1
YCbCr
3
Comp_2
YCbCr
3
uCom
MTV416
IN2
IN3
IN4
CXA2069
Comp_1
LR
2
AT/NT_S_Tune
r
OR1
656
Data[0:7]
TP/D1
8
2
YCbCr
20
H,V 2
FID
OR1
OR2
YCbCr
30
H,V
FID
Video Decoder
(UPD64015)
X-tal
(24.576M)
System CPLD
H,V
H,V
ADC
(MST3361)
FID
2
LPF LP
F
HV_PC
HV_pol
OR1
YCbCr
30
H,V
2
2
3
YCbCr
OR2
AT/NTSC Tuner
ATSC/NTSC/
OOB Tuner
V
RF
SW
Cable
ANT.
V
IF_AGC
2
nd
IF
–
(6M)
U-Com
SIF
X-tal
(25M)
POD
1394
Controller
(TSB43DA42)
(TPA
–
,TPB
–
) *2
4
D
OOB IF+/-
PI
PO
8
8
8
Add.
[0:13]
14
DRX / CRX
2
POD_TP[0:7]
CLK,VALID,SOP
KIA7029
74LCX244
Reset
HV,Hact
RGB
30
3
DOutClk
LVDS Tx
.
(THC63LVD103)
TX[0:4]
–
TXC
–
12
VCXO
27Mh
z
LGDPLL
(LGDT1901B
)
HD2_VDPClk
(74.25M)
HD2_SYS_CLK
RS-232C
(ST3232)
HDMI_SPDIF
SPDIF
System
CPLD
I2C Hub
(PCA9516)
IIC 1
EN[0:3(GPIO)]
4
CPU [PPC 405GPr]
- SDRAM Controller - Peripheral Controller - Local BUS I/F - Serial(2), GPIO, I2Cr
1.8V
Reg.
EEPROM
(AT24LC512
)
Voltage
Controller
LTC1470
VPP_SW
VPP_SW
Flag
VPP1
VPP
MNT_Out
LR
2
SIF
LR
2
Comp_2
LR
2
RGB(Phone)
LR
2
I2S Out
3
HD-2.4
ANALOG_L/R
BSS83 BSS83
8
2
RXD[0:2]
–
, RXCLK
–
DDC(I2C)
RGB
H,V,DE
3
30
RESET
HD2_MAIN_PWM
CPLD
IEP3
SPDIF_IN_BYPASS
AUDIO ADC
(CS5331)
I2S In
3
PWM
MODULATOR
(NSP2100A)
I2S
I2S_MCLK
PWM AMP
(TAS5122)
PWM_L/R
GS_Y_2069
GS_V_TU
MAIN_CVBS
SYNC
SEPARATOR
(MM1108XF)
ANALOG DE/
MULTIPLEXER
(74HCT4053)
U-COM
(PIC18F1220)
H,V
G_LINK_CONN
UART1_RX/TX
GEM_IR_OUT
Voltage
Comp.
(LM311M)
BUFFER
(MC33078)
MST33611_HDM
I
IIC 1
0xC2
IIC 1
0xC0
IIC 2
0xB8
IIC 2
0x
B
A
IIC 2
0x9C
IIC 3
0x1C
IIC 1
0xA6
IIC2
0x1E
IIC 4
0x
6
C
IIC 2
0x
9
C
IIC 4
0x90
2
11
IIC 2
IIC 3
IIC 4
M_MSP
4440
SIF
IIC 4
0x84
Video SW
(CXA2181)
EPF_RGB-PC
RGBHV
5
IN1
AT/NT_M_Tuner
Main
Sound Proc
(MSP4440)
IIC 4
0x
8
0
Sub
MSP
4458G
AT/NT Tuner
Rear L/R
Side L/R
I2S
(Main)
(Sub)
PDR 656[0:7]
1394_OUT_TP[0:7]
1394_IN_TP[0:7]
PVRsoc
(LGDT1303)
PC_TPOU
TI
CP_TPN1[0:7]
HD2_TP[0:7]
CP_TPN2[0:7]
HD-2.4
-TP De-Mux
- MPEG Decoding : MP@HL
-Format Converter
-Host I/F, Memory I/F
-Digital I/F
-NTSC Encoder
-AC-3 Decoder/SPDIF In/out
-IEP2
CY2305SC
HD2_NT2CLK
PVR_SYS_CLK
EPLD_CLK
DPLL_R[1:3]
HD2_ICE958_OUT
XDR_DATA_R/G/B[0:9]
PVRSoc
Sub
MSP4458G
SDRAM
32MByte
(8MB x4)
Peripheral Bus
64-Bit I/F
Control GPIO
Peripheral Bus
DDR
32Mb
SATA I/F
(SiI3512)
X-tal
(25M)
TX/RX P1,N1
TX/RX P2,N2
PCI Bus
PCI Bus
IIC 3
0x50
IIC 4
0x
8
8
VBI
Slicer
& IR (USA Only)
OOB/POD Controller (USA Only)
Flash Memory
16MB(8MBx2)
32Bit Bus I/F
IN3
IN6
HD2_REC_CVBS
CXA2069
EPF_L/R
A/V SW
(CXA2069)
HD2_CVBS_OUT
HD-II
SDRAM
64MB(32MBx2)
PWM AMP
(TAS5122)
LGDT3703
Main
VSB DATA
11
Filter(opt
)
(FMS6400)
Filter(opt
)
(FMS6400)
2
2
SDRAM
(1Mx
16Bit)
Video Decoder
(UPD64015)
X-tal
(24.576M)
SDRAM
(1Mx
16Bit)
2
EEPROMEEPROM
8
RXD[0:2]
–
, RXCLK
–
DDC(I2C)
EEPROMEEPROM
BSS83 BSS83
HDMI Rx
MST3361
PIC18F242
CPU
X-tal
(25M)
IIC 2
0xB2
LGDT3703
S_MSP
4458G
IF_AGC
2
nd
IF
–
(6M)
MUX
CPLD
V/Q _TP
PC_TPOUT2
IIC3
0x12
P_SW_2
LPF(OPT)
(FMS6403)
SYS
CPLD
CLK
CLK
EXT_IN_CLK
SYS
CPLD
CLK
SUB_656_CLK
656CLK
CY2309
CP_656_CLK
MUX
CPLD
CP_656[0-7]
CY2309
OR2
OR3
CPLD
OR3
OR3
HD2
DE
FID
74LCX244
PI_CLKB
PI_CLK
DRX / CRX
OOB_EN1_2
DRX / CRX
74LCX14
SEL
¥ Yellow Box
—
Show the
in/out connections
GS_Y_1
VCXO
33.33Mhz
CY2309SC
CPU_CLK
PCI_CLK_PVR
PCI_CLK_1394
PCI_CLK_SATA
AH_SPDIFCLK
HD2_DAC_SCK/LRCK
SPDIF Receiver.
(CS8415A)
DCR DVR BLOCK DIAGRAM
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