42LW5500-ZE, 42LW550T-ZE, 42LW550W-ZE, 42LW551C-ZE, 42LW5590-ZE (CHASSIS:LD12C) - LG TV Service Manual (repair manual). Page 43

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THE    SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS 
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE    SYMBOL MARK OF THE SCHEMETIC.
FRC_DQU[5]
FRC_DQU[0]
FRC_DQL[0]
FRC_DQU[7]
FRC_A[0]
FRC_DQL[1]
FRC_DQU[4]
FRC_A[6]
FRC_A[10]
FRC_A[4]
FRC_DQL[5]
FRC_A[2]
FRC_A[8]
FRC_A[9]
FRC_A[7]
FRC_A[1]
FRC_A[5]
FRC_A[3]
FRC_DQU[6]
FRC_A[11]
FRC_DQL[2]
FRC_A[12]
FRC_DQU[2]
FRC_A[13]
FRC_DQL[4]
FRC_DQL[3]
FRC_DQU[1]
FRC_DQL[7]
FRC_DQU[3]
FRC_DQL[6]
LVDS_TXD2P
SPI_DO
AVDD_LVDS_3.3V
LVDS_TXD3P
+1.26V_FRC
PWM1
C5208
0.1uF
R5210
10K
OPT
AVDD33
TXCCLKP
DVDD_DDR_1V
AVDD_PLL
TXD3P
R5211
10K
R5217
10K
OPT
R5231
100
R5226
100
TXB3P
TXDCLKN
TXC3N
LVDS_TXD3N
C5240
0.1uF
TXD2P
AVDD_PLL
SPI_SCLK
TXD4P
VDDC10
LVDS_TXD1P
TXA2N
LVDS_TXC1N
C5220
0.1uF
C5217
0.1uF
C5238
0.1uF
SCL2_+3.3V_URSA
TXDCLKP
VDDC10
C5210
22uF
10V
2D/3D_CTL
LVDS_TXA1P
C5239
0.1uF
+3.3V_FRC
C5233
0.1uF
R5212
10K
OPT
R5213
10K
LVDS_EXT_URSA5
FRC_DQSL
R5242
33
TXB3N
URSA_MODEL_OPT_1
LVDS_TXB1N
TXB0P
AVDD33
C5227
0.1uF
LVDS_TXB1P
LVDS_TXACLKP
TXB0N
LVDS_TXC0N
TXD2N
C5207
0.1uF
C5201
0.1uF
TXB1P
SPI_DI
C5232
0.1uF
R5251
33
R5208
10K
OPT
R5225
100
+1.5V_FRC_DDR
LVDS_TXA4N
R5237
1M
R5215
10K
OPT
VDD33
LVDS_TXC0P
C5225
0.1uF
DVDD_DDR_1V
SPI_SCLK
R5245
33
TXD4N
FRC_CASB
LVDS_TXC4N
C5231
0.1uF
+3.3V_FRC
TXC0P
TXC3P
R5204
10K
OPT
TXD0N
+3.3V_FRC
FRC_MCLK
P5201
12507WR-04L
URSA5_DEBUG
1
2
3
4
5
LVDS_TXD4P
SDA2_+3.3V_URSA
M1_SCLK
LVDS_TXB0N
R5209
10K
OPT
TXA1P
LVDS_TXC2P
TXD1P
TXB2N
SDA2_+3.3V_DB
C5205
0.1uF
FRC_DQL[0-7]
TXACLKP
LVDS_TXA1N
TXC2N
TXA0P
+3.3V_FRC
FRC_DQSU
URSA_MODEL_OPT_0
TXCCLKN
L5205
CIC21J501NE
FRC_RASB
SCL2_+3.3V_DB
M2_SCLK
LVDS_TXC2N
FRC_BA0
C5234
0.1uF
R5230
100
LVDS_TXDCLKP
TXA3N
LVDS_TXD1N
R5223
33
AVDD_PLL
LVDS_TXA2P
URSA_MODEL_OPT_0
TXB1N
FRC_DQSUB
SW5201
JS2235S
URSA5_DEBUG
3
2
1
4
5
6
FRC_WEB
TXA4P
PWM0
L5202
CIC21J501NE
R5203
10K
LVDS_TXA0N
GPIO[1]
LVDS_TXD0N
C5236
0.1uF
R5224
100
R5214
10K
LVDS_S7M-PLUS
C5215
10uF
6.3V
PWM0
C5219
0.1uF
TXD1N
LVDS_TXB3N
R5244
4.7K
R5206
10K
L/DIM_EDGE_42/47/55
SDA2_+3.3V_DB
GPIO[8]
M3_MOSI
R5234
100
L5206
CIC21J501NE
R5221
4.7K OPT
R5249
33
+1.5V_FRC_DDR
FRC_ODT
3D_SYNC
LVDS_TXD2N
R5216
10K
LVDS_TXCCLKP
M0_MOSI
LVDS_TXB4P
C5202
0.1uF
+3.3V_FRC
TXD3N
TXBCLKP
TXB4P
VDD33
TXC1P
TXC1N
R
5
2
3
8
0
LVDS_TXA0P
FRC_DQSLB
C5223
0.1uF
R5205
10K
L/DIM_EDGE_32/37
C5213
0.1uF
LVDS_TXBCLKP
AVDD_LVDS_3.3V
TXB4N
LVDS_TXB0P
L5204
CIC21J501NE
VDDC10
R5235
100
LVDS_TXB2P
3D_SYNC_RF
URSA_MODEL_OPT_1
LVDS_TXB4N
LVDS_TXA3N
TXD0P
+3.3V_FRC
TXA0N
L5201
CIC21J501NE
M0_SCLK
L_VS
TXA4N
R5202
22
URSA5_DEBUG
2D/3D_CTL
R5232
100
+1.26V_FRC
SDA2_3.3V
M3_SCLK
TXB2P
AVDD_LVDS_3.3V
FRC_DML
TXC4N
LVDS_TXB2N
LVDS_TXA3P
R5250
33
SPI_CS
L5203
CIC21J501NE
TXC2P
LVDS_TXC3N
FRC_A[0-13]
C5209
0.1uF
SPI_DO
R
5
2
4
1
0
LVDS_TXDCLKN
R5248
33
R
5
2
3
9
0
LVDS_TXCCLKN
R5218
10K
OPT
R5207
10K
C5216
0.1uF
SPI_CS
M1_MOSI
TXC4P
R5229
100
R5227
100
C5204
0.1uF
+1.5V_FRC_DDR
TXC0N
+3.3V_FRC
TXA3P
LVDS_TXACLKN
C5203
0.1uF
TXBCLKN
FRC_BA1
R
5
2
4
0
0
R5247
33
R5233
100
LVDS_TXC3P
LVDS_TXC4P
URSA_MODEL_OPT_2
LVDS_TXBCLKN
LVDS_TXC1P
LVDS_TXA4P
VDD33
FRC_DQU[0-7]
R5228
100
M2_MOSI
R5253
33
3D-SG
C5228
0.1uF
URSA_MODEL_OPT_2
C5206
0.1uF
C5214
0.1uF
SCL2_3.3V
FRC_MCLKB
SDA2_+3.3V_URSA
TXACLKN
FRC_DMU
FRC_CKE
R5201
22
URSA5_DEBUG
TXA2P
LVDS_TXB3P
R
5
2
3
6
0
R5246
10K
PWM1
TXA1N
LVDS_TXA2N
LVDS_TXD0P
+3.3V_FRC
SCL2_+3.3V_URSA
AVDD33
LVDS_TXD4N
GPIO[1]
R5222
33
R5252
3.3K
SCL2_+3.3V_DB
R5220
4.7K OPT
C5211
22uF
10V
SPI_DI
GPIO[8]
FRC_BA2
C5243
0.22uF
6.3V
C5244
0.22uF
6.3V
C5245
0.22uF
6.3V
R5258
0
URSA5_MP
R5260
0
OPT
R5261
0
OPT
R5259
0
URSA5_MP
X5201
24MHz
C5242
13pF
C5241
13pF
C5246
22uF
10V
FRC_DDR3_RESETB
C5247
1uF
6.3V
IC5202
W25X20BVSNIG
URSA5_FLASH_WINBOND_2M
3
WP
2
DO
4
GND
1
CS
5
DIO
6
CLK
7
HOLD
8
VCC
IC5202-*1
MX25L2006EM1I-12G, HF
URSA5_FLASH_MACRONIX_2M
3
WP
2
SO/SIO1
4
GND
1
CS
5
SI/S
6
SCL
7
HOL
8
VCC
+3.3V_FRC
R5254
4.7K
URSA5_UO2_RESET
Q5201
2SC3052
URSA5_UO2_RESET
E
B
C
R5255
22K
URSA5_UO2_RESET
FRC_RESET
R5243
33
URSA5_UO3_RESET
C5212
4.7uF
16V
URSA5_UO2_RESET
R5219
10K
OPT
Q5202
AO3407A
URSA5_UO2_RESET
G
D
S
R5256
10K
OPT
R5262
2.2K
URSA5_UO2_RESET
IC5201
LGE7303C
DDR3_A0/DDR2_NC
P14
DDR3_A1/DDR2_A8
G15
DDR3_A2/DDR2_NC
N14
DDR3_A3/DDR2_A10
L15
DDR3_A4/DDR2_A2
H15
DDR3_A5/DDR2_A3
L14
DDR3_A6/DDR2_A4
G14
DDR3_A7/DDR2_A5
N12
DDR3_A8/DDR2_A6
G13
DDR3_A9/DDR2_A9
N13
DDR3_A10/DDR2_RASZ
H14
DDR3_A11/DDR2_A11
F15
DDR3_A12/DDR2_A0
H13
DDR3_A13/DDR2_A12
P13
DDR3_BA0/DDR2_BA2
M12
DDR3_BA1/DDR2_CASZ
H12
DDR3_BA2/DDR2_A1
L13
DDR3_MCLK/DDR2_MCLK
F16
DDR3_MCLKZ/DDR2_MCLKZ
F17
DDR3_CKE/DDR2_ODT
J13
DDR3_ODT/DDR2_CKE
K12
DDR3_RASZDDR2_WEZ
L12
DDR3_CASZ/DDR2_BA1
K13
DDR3_WEZ/DDR2_BA0
K14
DDR3_RESET/DDR2_A7
M14
DDR3_DQSL/DDR2_DQSL
N16
DDR3_DQSU/DDR2_DQSU
M17
DDR3_DQSBL/DDR2_DQSBL
M16
DDR3_DQSBU/DDR2_DQSBU
M15
DDR3_DQML/DDR2_DQU5
J15
DDR3_DQMU/DDR2_DQU4
R16
DDR3_DQL0/DDR2_DQU3
R17
DDR3_DQL1/DDR2_DQL0
H17
DDR3_DQL2/DDR2_DQL6
R15
DDR3_DQL3/DDR2_DQL7
J17
DDR3_DQL4/DDR2_DQL3
T17
DDR3_DQL5/DDR2_DQL2
H16
DDR3_DQL6/DDR2_DQL1
T15
DDR3_DQL7/DDR2_DQL5
G16
DDR3_DQU0/DDR2_DQU7
K15
DDR3_DQU1/DDR2_DQML
N15
DDR3_DQU2/DDR2_DQU2
K17
DDR3_DQU3/DDR2_DQU6
P17
DDR3_DQU4/DDR2_NC
L17
DDR3_DQU5/DDR2_DQU1
P16
DDR3_DQU6/DDR2_DQU0
K16
DDR3_DQU7/DDR2_DQMU
P15
I2CM_SCL
D14
I2CM_SDA
D15
I2CS_SCL
P1
I2CS_SDA
P2
DDR3_NC/DDR2_A13
F14
DDR3_NC/DDR2_DQL4
T16
VSS_1
D6
VSS_2
D7
VSS_3
D8
VSS_4
D9
VSS_5
E6
VSS_6
E7
VSS_7
E8
VSS_8
E9
VSS_9
E10
VSS_10
E16
VSS_11
F3
VSS_12
F6
VSS_13
F7
VSS_14
F8
VSS_15
F9
VSS_16
G1
VSS_17
G2
VSS_18
G4
VSS_19
G5
VSS_20
G6
VSS_21
G7
VSS_22
G8
VSS_23
G9
VSS_24
G17
VSS_25
H1
VSS_26
H2
VSS_27
H4
VSS_28
H5
VSS_29
H6
VSS_30
H7
VSS_31
H8
VSS_32
H9
VSS_33
H10
VSS_34
H11
VSS_35
J4
VSS_36
J5
VSS_37
J6
VSS_38
J7
VSS_39
J8
VSS_40
J9
VSS_41
J10
VSS_42
J11
VSS_43
J12
VSS_44
J14
VSS_45
J16
VSS_46
K4
VSS_47
K5
VSS_48
K6
VSS_49
K7
VSS_50
K8
VSS_51
K11
VSS_52
L6
VSS_53
L7
VSS_54
L8
VSS_55
L11
VSS_56
L16
VSS_57
M6
VSS_58
M7
VSS_59
M8
VSS_60
M11
VSS_61
M13
VSS_62
N6
VSS_63
N7
VSS_64
N8
VSS_65
N17
VSS_66
P3
VSS_67
P4
VSS_68
P5
VSS_69
P6
VSS_70
P7
VSS_71
P12
VSS_72
U16
NC
L9
HW_RESET
J3
TESTPIN_1
D1
TESTPIN_2
D2
TESTPIN_3
D3
TESTPIN_4
E1
TESTPIN_5
E2
TESTPIN_6
E3
TESTPIN_7
F1
TESTPIN_8
F2
M0_SCLK
C17
M0_MOSI
D16
M1_SCLK
D17
M1_MOSI
E15
M2_SCLK
E14
M2_MOSI
E13
M3_SCLK
E12
M3_MOSI
F13
SPI_CK
T9
SPI_CZ
U10
SPI_DI
U9
SPI_DO
T10
TXA0P/GCLK6/BLUE[7]
C8
TXA0N/GCLK5/BLUE[6]
C9
TXA1P/OPT_N/LK3/BLUE[9]
B8
TXA1N/FLK/BLUE[8]
A8
TXA2P/GREEN[1]
A7
TXA2N/OPT_P/LK2/GREEN[0]
B7
TXACLKP/RLV0N/GREEN[3]
C6
TXACLKN/RLV0P/GREEN[2]
C7
TXA3P/RLV1N/GREEN[5]
B6
TXA3N/RLV1P/GREEN[4]
A6
TXA4P/RLV2N/GREEN[7]
A5
TXA4N/RLV2P/GREEN[6]
B5
TXB0P/RLV3N/GREEN[9]
C4
TXB0N/RLV3P/GREEN[8]
C5
TXB1P/RLVCLKN/RED[1]
B4
TXB1N/RLVCLKP/RED[0]
A4
TXB2P/RLV4P/RED[3]/EPI_A3P
A3
TXB2N/RLV4N/RED[2]/EPI_A3N
B3
TXBCLKP/RLV5N/RED[5]/EPI_A2P
C2
TXBCLKN/RLV5P/RED[4]/EPI_A2N
C3
TXB3P/RLV6N/RED[7]/EPI_A1P
B2
TXB3N/RLV6P/RED[6]/EPI_A1N/
A2
TXB4P/RLV7N/RED[9]/EPI_A0P
C1
TXB4N/RLV7P/RED[8]/EPI_A0N
B1
TXC0P/SOE
C16
TXC0N/POL
B17
TXC1P/GSP_R
B16
TXC1N/GSP/VST
A16
TXC2P/GOE/GCLK1
A15
TXC2N/GSC/GCLK3
B15
TXCCLKP/LLV0N
C14
TXCCLKN/LLV0P
C15
TXC3P/LLV1N
B14
TXC3N/LLV1P
A14
TXC4P/LLV2N
A13
TXC4N/LLV2P
B13
TXD0P/LLV3N
C12
TXD0N/LLV3P
C13
TXD1P/LLVCLKN
B12
TXD1N/LLVCLKP
A12
TXD2P/LLV4N/EPI_B3P
A11
TXD2N/LLV4P/EPI_B3N
B11
TXDCLKP/LLV5N/BLUE[1]/EPI_B2P
C10
TXDCLKN/LLV5P/BLUE[0]/EPI_B2N
C11
TXD3P/LLV6N/BLUE[3]
B10
TXD3N/LLV6P/BLUE[2]/EPI_B1N
A10
TXD4P/LLV7N/BLUE[5]/EPI_B0P
A9
TXD4N/LLV7P/BLUE[4]/EPI_B0N
B9
MOD_GPIO0/VDD_ODD/HSYNC
D10
MOD_GPIO1/VDD_EVEN/VSYNC
D11
MOD_GPIO2/PWM13/GCLK4/LCK
D12
MOD_GPIO3/PWM14/GCLK2/LDE
D13
PWM0/SCAN_BLK1
U12
PWM1/SCAN_BLK2
T12
LPLL_FBCLK
G3
LPLL_OUTCLK
E17
LPLL_REFIN
H3
AVDD_1
F4
AVDD_2
F5
AVDD_DDR_C_1
F10
AVDD_DDR_C_2
G10
AVDD_DDR_D_1
F11
AVDD_DDR_D_2
F12
AVDD_DDR_D_3
G11
AVDD_DDR_D_4
G12
AVDD_LVDS3.3V_1
D4
AVDD_LVDS3.3V_2
D5
AVDD_LVDS3.3V_3
E4
AVDD_LVDS3.3V_4
E5
AVDD_MPLL3.3V
M5
AVDD_LPLL3.3V
L4
AVDD_PLL3.3V
L5
AVDDL_MOD1.26V
K10
DVDD_DDR_1.26V
L10
DVDD_HF1.26V
K9
VD33_1
M4
VD33_2
N4
VD33_3
N5
VDDC_1.26V_1
M9
VDDC_1.26V_2
M10
VDDC_1.26V_3
N9
VDDC_1.26V_4
N10
VDDC_1.26V_5
N11
VDDC_1.26V_6
P10
VDDC_1.26V_7
P11
RXBCLKP
R2
RXBCLKN
R3
RXB0P
R4
RXB0N
R5
RXB1P
T4
RXB1N
U4
RXB2P
U3
RXB2N
T3
RXB3P
T2
RXB3N
U2
RXB4P
T1
RXB4N
R1
RXACLKP
R6
RXACLKN
R7
RXA0P
R8
RXA0N
R9
RXA1P
T8
RXA1N
U8
RXA2P
U7
RXA2N
T7
RXA3P
T6
RXA3N
U6
RXA4P
U5
RXA4N
T5
XTALO
J1
XTALI
J2
GPIO0/(UART_RX/S_PIF_DA0)
R13
GPIO1
P9
GPIO2/(S_PIF_CLK)
T13
GPIO3/(LTD_DA1)
U15
GPIO4/(LTD_DE)
R14
GPIO5/(LTD_CLK)
K2
GPIO6/(LTD_DA0)
K1
GPIO7(3D_FLAG)
T14
GPIO8
P8
GPIO9/(UART_TX/S_PIF_DA1)
U14
GPIO10/(S_PIF_FC)
U13
GPIO11/(S_PIF_CS)
R12
VSYNC_LIKE
E11
M_S_PIF_CLK
N2
M_S_PIF_CS
M1
M_S_PIF_DA0
N1
M_S_PIF_DA1
N3
M_S_PIF_FC
M3
S_M_PIF_CLK
L1
S_M_PIF_CS
M2
S_M_PIF_DA0
L2
S_M_PIF_DA1
K3
S_M_PIF_FC
L3
SOFT_RST_L
R10
SOFT_RST_R
T11
OP_SYNC_L
R11
OP_SYNC_R
U11
FRC block
MStar URSA5
55
52
2010. 08.18
L/DIM_10BLOCK
D13
GPIO1 : HI => B8/94, LOW => B4/98
LOW
LVDS_S7M_PLUS
MODEL_OPT_0
MODEL_OPT_3
Debugging for URSA5
CHIP_CONF : {GPIO8, PWM1, PWM0}
CHIP_CONF = 3’d5 : boot from interal SRAM
CHIP_CONF = 3’d6 : boot from EEPROM
CHIP_CONF = 3’d7 : boot from SPI Flash
PIN NO.
[SPI FLASH(2Mbit)]
LVDS_EXT_URSA5 
D11
NON USED 
BCM35230 LVDS CHC/D
D10
D12
RESERVED
MODEL_OPT_2
MODEL OPTION
(VDDP)
HIGH
PIN NAME
RESERVED
PLACE TERMINATION RESISTORS CLOSE TO URSA5
MODEL_OPT_1
URSA5 CONFIGURATION
Place Close to Bead
URSA5 H/W OPTION
L/DIM_16BLOCK
RESERVED
RESERVED
Display
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