Read LG 42LB5DC (CHASSIS:LA64A) Service Manual online
- 29 -
EPM570F256
Pro:Idiom
FPGA
Parallel
To Serial
Byte To
Bit Sync
I2S
nput
Mux
Video
12bit to 24bit
ICS512
X 8 PLL
CLK
SYNC
VALID
ERROR
DATA[0-7]
8XCLK
TO D2A
I2S FROM SIl9011
I2S FROM 7411
MCLK
LRCLK SCLK
DATA
CPLD Connection & Function Diagram
EBI bus
extension
8bit to 16bit
I2C
Mux
MCLK
LRCLK
SCLK
DATA
SPDIF FROM D2A
SPDIF FROM MSP
SPDIF FROM 7411
SPDIF
Output
Mux
SPDIF OUT
I2S TO D2A
Bus Tristate Control
Enable
V-sync
H-sync
DATA[0-12]
DATA[0-8]
YCbCr
Out FROM 7411
BUS I/F FROM D2A
BUS I/F TO 7411
OE
WAIT
CLK
CS
WE
DATA[0-24]
DATA[0-16]
SCL_D2A from D2A
SDA_D2A from D2A
ADDR[0-3]
24bit Data TO Cortez
Mux
& Bypass
Selection Logic
SCL from Cortez
SDA from Cortez
CPLD SCL
CPLD SDA
TS FROM D2A
CLK
SYNC
VALID
DATA
Serial
To
Parell
CLK
SYNC
VALID
DATA[0-7]
GPIO & ETC
TO 7411
Click on the first or last page to see other 42LB5DC (CHASSIS:LA64A) service manuals if exist.