Read LG 32LH35FD (CHASSIS:LJ91A) Service Manual online
[E1]
[D1]
[L9]
[N5]
[N4]
[N12]
[N13]
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
2008.10.15
Mstar FRC
BCM (BRAZIL VENUS)
URSA_D+[2]
URSA_DQ[26]
URSA_B-[1]
URSA_CCK+
URSA_DQ[9]
URSA_DQ[28]
URSA_A-[4]
URSA_B-[3]
URSA_DQ[17]
URSA_C-[3]
URSA_DQ[0-31]
URSA_DQ[4]
URSA_B-[0]
URSA_A-[2]
URSA_DQ[5]
URSA_A[1]
URSA_DQ[23]
URSA_A[12]
URSA_B+[2]
URSA_ACK-
URSA_DQ[1]
URSA_C+[2]
URSA_DCK-
URSA_DQ[31]
URSA_DQ[25]
URSA_A[11]
URSA_BCK+
URSA_DQ[8]
URSA_DQ[0]
URSA_D+[3]
URSA_A[6]
URSA_A[7]
URSA_A[4]
URSA_A[9]
URSA_DQ[13]
URSA_D+[0]
URSA_C+[1]
URSA_DQ[22]
URSA_B+[1]
URSA_A+[1]
URSA_D-[1]
URSA_ACK+
URSA_A-[0]
URSA_DQ[29]
URSA_DQ[20]
URSA_DQ[24]
URSA_A[2]
URSA_DCK+
URSA_DQ[30]
URSA_A[8]
URSA_C-[0]
URSA_B+[4]
URSA_DQ[12]
URSA_C-[4]
URSA_DQ[18]
URSA_A+[4]
URSA_C+[4]
URSA_B+[0]
URSA_A-[3]
URSA_DQ[7]
URSA_D+[1]
URSA_A-[1]
URSA_D-[0]
URSA_D-[3]
URSA_A+[3]
URSA_A[10]
URSA_C+[0]
URSA_C-[1]
URSA_A+[0]
URSA_B-[2]
URSA_DQ[6]
URSA_DQ[14]
URSA_D-[4]
URSA_A[0]
URSA_DQ[10]
URSA_DQ[2]
URSA_D+[4]
URSA_B-[4]
URSA_DQ[16]
URSA_DQ[15]
URSA_DQ[27]
URSA_DQ[19]
URSA_A[5]
URSA_A+[2]
URSA_CCK-
URSA_C+[3]
URSA_DQ[3]
URSA_DQ[11]
URSA_B+[3]
URSA_C-[2]
URSA_A[3]
URSA_DQ[21]
URSA_BCK-
URSA_D-[2]
C
2
7
3
5
0.1uF
R2721
0 OPT
R2703
56
R2709
1K
C2710
10uF
10V
10uF
10V
C
2
7
3
4
0
.
1
u
F
+3.3V_MEMC
C2729
0.1uF
URSA_DQSB0
009:Y12
TX_1_DATA0_N
C2726
0.1uF
M_XTALO
008:AF11
C
2
7
4
1
0
.
1
u
F
M_XTALI
008:P27
C
2
7
4
3
0
.
1
u
F
TX_0_DATA3_P
R2710
56
C
2
7
4
5
0
.
1
u
F
M_SPI_DO
008:AF6
C
2
7
4
7
0
.
1
u
F
TX_1_DATA1_N
TX_0_DATA1_P
C2752
0.1uF
TX_1_CLK_P
C
2
7
4
6
0
.
1
u
F
R2732
100
+3.3V_MEMC
C2716
0.1uF
16V
C2714
0.1uF
16V
URSA_DQM2
009:Q13
URSA_DQSB3
009:Q12
R2704
56
+3.3V_MEMC
C2715
0.1uF
URSA_C+[0-4],URSA_C-[0-4],URSA_CCK+,URSA_CCK-
008:AE17
C2703
22uF
16V
22uF
16V
TX_1_DATA0_P
ISP_RXD_TR
001:L5
R2733
100
R2729
100
C
2
7
4
2
0
.
1
u
F
URSA_MCLKZ1
009:Y15
URSA_DQS1
009:Y13
M_SPI_CK
008:Y10
L2704
BLM18PG121SN1D
R2713
1K
OPT
URSA_ODT
009:Q15;009:Y15
R2701
2.2K
ENG
LVDS_SEL
TX_0_DATA4_P
IC2701
LGE7329A
LH50_90_ONLY
E1
SDAS
D1
SCLS
F1
GPIO[8]
G1
GPIO[9]
K8
GND_14
E5
VDDC_1
E2
GPIO[10]
F2
GPIO[11]
F3
GPIO[12]
G2
GPIO[13]
M4
GPIO[22]
M5
GPIO[23]
G3
GPIO[14]
E4
GPIO[15]
F4
GPIO[16]
G4
GPIO[17]
H4
GPIO[18]
J4
GPIO[19]
K4
GPIO[20]
L4
GPIO[21]
J6
VDDP_2
H9
GND_7
F6
VDDC_2
H1
MDATA[20]
H2
MDATA[19]
H3
MDATA[17]
J1
MDATA[22]
J2
MDATA[27]
J3
MDATA[28]
K1
MDATA[25]
K2
MDATA[30]
K6
AVDD_DDR_2
K3
DQM[3]
L1
DQM[2]
J8
GND_10
L2
DQS[2]
L3
DQSB[2]
L6
AVDD_DDR_4
L8
VDDP_3
H10
GND_8
M1
DQS[3]
M2
DQSB[3]
L7
AVDD_DDR_5
M3
MDATA[31]
N1
MDATA[24]
J9
GND_11
N2
MDATA[26]
N3
MDATA[29]
L10
AVDD_DDR_6
P1
MDATA[23]
R1
MDATA[16]
T1
MDATA[18]
T2
MDATA[21]
R2
MCLK[0]
P2
MCLKZ[0]
G7
GND_1
L9
AVDD_MEMPLL
N5
MVREF
N4
ODT
T3
RASZ
R3
CASZ
P3
MADR[0]
T4
MADR[2]
R4
MADR[4]
J10
GND_12
P4
MADR[6]
T5
MADR[8]
R5
MADR[11]
P5
WEZ
T6
BADR[1]
R6
BADR[0]
P6
MADR[1]
T7
MADR[10]
L11
AVDD_DDR_7
R7
MADR[5]
P7
MADR[9]
T8
MADR[12]
R8
MADR[7]
P8
MADR[3]
N8
MCLKE
K10
GND_16
F7
VDDC_3
T9
MDATA[4]
R9
MDATA[3]
K7
GND_13
P9
MDATA[1]
T10
MDATA[6]
K11
AVDD_DDR_3
R10
MDATA[11]
P10
MDATA[12]
T11
MDATA[9]
R11
MDATA[14]
J11
AVDD_DDR_1
P11
DQM[1]
T12
DQM[0]
R12
DQS[0]
P12
DQSB[0]
H11
VDDP_1
T13
DQS[1]
R13
DQSB[1]
P13
MDATA[15]
T14
MDATA[8]
R14
MDATA[10]
P14
MDATA[13]
T15
MDATA[7]
R15
MDATA[0]
P15
MDATA[2]
T16
MDATA[5]
R16
MCLK[1]
P16
MCLKZ[1]
N9
GPIO[26]
N10
GPIO[27]
N11
GND_17
M11
RESET
G6
VDDC_4
N12
GPIO[28]
N13
GPIO[29]
N14
GPIO[30]
L13
SCK
M13
SDI
M12
SDO
K13
CSZ
L12
PWM1
K12
PWM0
J13
GPIO[0]
H13
GPIO[1]
G13
GPIO[2]
F13
GPIO[3]
E13
GPIO[4]
F12
GPIO[5]
D14
GPIO[6]
E12
GPIO[7]
N6
GPIO[24]
H6
VDDC_5
N15
LVD4M
N16
LVD4P
M14
LVD3M
M15
LVD3P
F8
AVDD_33_1
M16
LVDCKM
L16
LVDCKP
L15
LVD2M
L14
LVD2P
G9
GND_3
K14
LVD1M
J14
LVD1P
J16
LVD0M
J15
LVD0P
H15
LVC4M
H16
LVC4P
H14
LVC3M
G14
LVC3P
G16
LVCCKM
G15
LVCCKP
F15
LVC2M
F16
LVC2P
F14
LVC1M
E14
LVC1P
E16
LVC0M
E15
LVC0P
G10
GND_4
F9
AVDD_33_2
D16
LVB4M
D15
LVB4P
C16
LVB3M
B16
LVB3P
A16
LVBCKM
A15
LVBCKP
B15
LVB2M
C15
LVB2P
D2
GPIO_3
E3
GPIO_10
E10
GPIO_11
D10
GPIO_7
D8
GPIO_5
D12
REXT
C14
LVB1M
C13
LVB1P
A13
LVB0M
B13
LVB0P
D7
GPIO_4
D9
GPIO_6
B12
LVA4M
A12
LVA4P
C12
LVA3M
C11
LVA3P
A11
LVACKM
B11
LVACKP
B10
LVA2M
A10
LVA2P
C10
LVA1M
C9
LVA1P
A9
LVA0M
B9
LVA0P
F10
AVDD_PLL
G8
GND_2
D11
GPIO_8
D13
GPIO_9
E11
GPIO_12
N7
GPIO[25]
D6
SCLM
D5
SDAM
A14
GPIO_1
B14
GPIO_2
D3
XIN
D4
XOUT
K16
GPIO_14
K15
GPIO_13
H7
GND_5
G11
AVDD_LVDS_2
B8
RO0N
A8
RO0P
C8
RO1N
C7
RO1P
A7
RO2N
B7
RO2P
B6
ROCKN
A6
ROCKP
C6
RO3N
C5
RO3P
A5
RO4N
B5
RO4P
H8
GND_6
F11
AVDD_LVDS_1
B4
RE0N
A4
RE0P
C4
RE1N
C3
RE1P
A3
RE2N
B3
RE2P
B2
RECKN
A2
RECKP
C2
RE3N
C1
RE3P
A1
RE4N
B1
RE4P
GND_9
J7
GND_15 K9
+3.3V_MEMC
URSA_MCLK1
009:Y16
C2755
10uF
10V
10V
TX_0_CLK_P
TX_0_CLK_N
+3.3V_MEMC
C2731
0.1uF
URSA_BA0
009:T10;009:V11
C2722
0.1uF
R2711
56
L2703
BLM18PG121SN1D
URSA_DQS3
009:Q13
X2701
12MHz
URSA_CASZ
009:S17;009:W17
M_SPI_CZ
008:AF6
M_SPI_DO
008:Y11
TX_1_DATA3_N
SDA3_3.3V
9:I4
R2737
10K
URSA_BA1
009:T10;009:V11
M_XTALI
008:AJ11
URSA_MCLKZ
009:Q15
R2724
100
+3.3V_MEMC
M_XTALO
008:P27
SCL3_3.3V
9:I4
URSA_DQ[0-31]
009:D21;009:AL21
C
2
7
0
6
0
.
1
u
F
C2750
0.1uF
C2756
10uF
10V
TX_1_CLK_N
C2754
10uF
C
2
7
3
7
0.1uF
TX_0_DATA3_N
R2708
1K
OPT
R2705
10K
+1.26V_MEMC
URSA_WEZ
009:T10;009:V11
L2707
BLM18PG121SN1D
R2738
1K
URSA_DQS2
009:Q13
C2727
10uF
10V
C2751
0.1uF
R2725
100
R2734
100
TX_0_DATA2_P
IC2702
W25X20AVSNIG
3
WP
2
DO
4
GND
1
CS
5
DIO
6
CLK
7
HOLD
8
VCC
C2708
22uF
16V
R2712
1K
TX_0_DATA2_N
R2718
10K
R2715
0
R2720
1M
L2702
BLM18PG121SN1D
R2723
100
TX_1_DATA3_P
C2744
1uF
C
2
7
0
2
0
.
1
u
F
URSA_B+[0-4],URSA_B-[0-4],URSA_BCK+,URSA_BCK-
008:AM24
C2723
0.1uF
+3.3V_ST
C2748
0.1uF
URSA_DQM3
009:Q13
R2719
10K
C
2
7
3
6
0.1uF
R2741
1K
OPT
URSA_DQSB2
009:Q12
URSA_D+[0-4],URSA_D-[0-4],URSA_DCK+,URSA_DCK-
008:AL17
C2712
10uF
URSA_A[0-12]
009:U20
R2726
100
R2727
100
C2732
0.1uF
M_SPI_CK
008:AK5
R2740
1K
+3.3V_MEMC
+5.0V
TX_0_DATA0_P
C2709
10uF
L2705
BLM18PG121SN1D
+1.8V_MEMC
R2730
100
C2720
0.1uF
C2721
0.1uF
M_SPI_CZ
008:Y11
ISP_TXD_TR
001:L5
C
2
7
3
9
0.1uF
C
2
7
0
4
0
.
1
u
F
L2706
BLM18PG121SN1D
C2749
0.1uF
C2707
0.1uF
0.1uF
R2739
1K
OPT
R2717
100
C2725
1uF
M_SPI_DI
008:AK5
ISP_TXD_TR
B6
C2753
0.1uF
TX_1_DATA1_P
R2722
0 OPT
P2701
TJC2508-4A
ENG
1
2
3
4
C
2
7
3
3
0
.
1
u
F
ISP_RXD_TR
B6
R2735
0
URSA_DQSB1
009:Y12
URSA_DQM1
009:Y13
TX_0_DATA4_N
R2706
1K
OPT
C2730
10uF
URSA_MCLK
009:Q16
C2711
0.1uF
C2719
0.1uF
+3.3V_MEMC
TX_1_DATA2_P
L2701
BLM18PG121SN1D
R2702
2.2K
ENG
URSA_RASZ
009:S17;009:W17
C
2
7
1
8
0
.
1
u
F
C
2
7
3
8
0.1uF
R2736
820
URSA_DQS0
009:Y13
BIT_SEL
R2714
0
C2713
0.1uF
URSA_MCLKE
009:T10;009:V11
+3.3V_MEMC
TX_0_DATA0_N
R2731
100
C
2
7
4
0
0
.
1
u
F
TX_1_DATA4_P
C2701
10uF
R2728
100
URSA_A+[0-4],URSA_A-[0-4],URSA_ACK+,URSA_ACK-
008:AF25
URSA_DQM0
009:Y13
C2705
10uF
C2728
0.1uF
M_SPI_DI
008:Y11
TX_0_DATA1_N
MEMC_RESET
001:AB21
R2716
100
R2707
1K
AR2705
0
1/16W
LH50_90_ONLY
AR2702
0
1/16W
LH50_90_ONLY
AR2704
0
1/16W
LH50_90_ONLY
AR2706
0
1/16W
LH50_90_ONLY
AR2703
0
1/16W
LH50_90_ONLY
TX_1_DATA2_N
TX_1_DATA4_N
LVDS_TX_0_DATA2_P
7:E7
LVDS_TX_0_CLK_N
7:E7
LVDS_TX_0_DATA0_N
7:E7
LVDS_TX_0_DATA0_P
7:E7
LVDS_TX_0_DATA1_N
7:E7
LVDS_TX_0_DATA2_N
7:E7
LVDS_TX_0_DATA1_P
7:E7
LVDS_TX_0_CLK_P
7:E7
LVDS_TX_1_DATA1_N
7:D7
LVDS_TX_0_DATA3_N
7:E7
LVDS_TX_0_DATA3_P
7:E7
LVDS_TX_1_DATA1_P
7:D7
LVDS_TX_1_DATA2_P
7:D7
LVDS_TX_1_DATA0_N
7:D7
LVDS_TX_1_CLK_P
7:D7
LVDS_TX_1_CLK_N
7:D7
LVDS_TX_1_DATA2_N
7:D7
LVDS_TX_0_DATA4_N
7:E7
LVDS_TX_1_DATA0_P
7:D7
LVDS_TX_0_DATA4_P
7:E7
TX_1_DATA4_P
TX_1_DATA2_N
TX_1_DATA1_N
TX_1_DATA0_P
TX_0_DATA4_N
TX_0_DATA2_P
TX_1_DATA4_N
TX_0_CLK_N
TX_0_DATA3_N
TX_1_CLK_P
TX_0_DATA0_N
TX_0_CLK_P
TX_0_DATA2_N
TX_1_DATA3_N
TX_1_DATA3_P
TX_1_DATA0_N
TX_1_CLK_N
TX_1_DATA2_P
TX_0_DATA1_N
TX_0_DATA1_P
TX_0_DATA4_P
TX_0_DATA0_P
TX_1_DATA1_P
TX_0_DATA3_P
LVDS_TX_1_DATA3_P
7:D7
LVDS_TX_1_DATA4_P
7:D7
LVDS_TX_1_DATA4_N
7:D7
LVDS_TX_1_DATA3_N
7:D7
AR2701
0
1/16W
LH50_90_ONLY
C2717
20pF
C2724
20pF
7
15
* ISP Port for MEMC
HIGH
HIGH
GPIO8
I2C
HIGH
PWM1
HIGH
GPIO12 GPIO14
Non M+S LVDS LOW LOW
M+S 42" Mini LVDS LOW HIGH
M+S 47" Mini LVDS HIGH LOW
M+S 37" Mini LVDS HIGH HIGH
Non M+S LVDS LOW LOW
M+S 42" Mini LVDS LOW HIGH
M+S 47" Mini LVDS HIGH LOW
M+S 37" Mini LVDS HIGH HIGH
XTAL
HIGH
HIGH
EEPROM
PWM0
LOW
HIGH
PI Result
SPI FLASH
PI Result
LOW
SPI
This page is all LH50/90_ONLY option
A
B
C
D
E
F
G
H
I
J
1
2
3
4
5
6
7
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