Read LG 32LD540 / 32LD540 / 32LD541 / 32LD570 / 32LD575 (CHASSIS:LD01B) Service Manual online
5
5
4
4
3
3
2
2
1
1
D
D
C
C
B
B
A
A
DDR2 rules for 32-bit interface:
VREF on SDRAM -- Place high-quality ceramic bypass caps close to their corresponding VREF balls
as shown on the next sheet of the schematic.
as shown on the next sheet of the schematic.
Trace Impedances -
60 ohms +/- 10% except as noted
CLK / CLKb
DQS / DQSb
DQS / DQSb
100 ohms +/- 10% differential
100 ohms +/- 10% differential
100 ohms +/- 10% differential
All traces should have >= 3:2 spacing ratio from the reference GND/PWR layer.
(e.g. 7.5 mil line-to-line spacing or more for a 5 mil dielectric thickness)
(e.g. 7.5 mil line-to-line spacing or more for a 5 mil dielectric thickness)
Terminations and Capacitors -
CLK / CLKb -- Place 100 ohm resistor between CLK and CLKb lines at end of traces by DDR RAM.
Address / Control -- Place parallel termination resistors/rpacks at end of daisy chains by SDRAM, or if
routes are T's then place at branch of T with stubs < 0.200". Termination resistors may be swapped to
improve routing.
routes are T's then place at branch of T with stubs < 0.200". Termination resistors may be swapped to
improve routing.
JEDEC has defined a common landing pattern (CLP) for use with different package options of DDR2 chips.
By using the CLP, a PCB can accommodate all DDR2 device configurations and will be compatible with
most package options,
By using the CLP, a PCB can accommodate all DDR2 device configurations and will be compatible with
most package options,
VREF0 / VREF1 -- Place voltage divider resistors and associated capacitors close to their
corresponding balls on the BCM355x chip. Use high-quality ceramic capacitors.
corresponding balls on the BCM355x chip. Use high-quality ceramic capacitors.
BCM355x pads for DQ / DQS / DM can select ODT impedance of 60 or 120 ohms.
Chip Placement -
Routing -
DDR_VREF0 and DDR_VREF1: Route as 30 mil trace
Place two DDR2 chips on the top side and tuck the DDR2 chips as close
to BCM355X DDR2 interface as possible.
to BCM355X DDR2 interface as possible.
Trace lengths -
CLK / CLKb
DQS / DQSb
DQ / DQM
All other
DQS / DQSb
DQ / DQM
All other
< 2" total length, delta in each pair < 0.1"
< 1.5" total length, delta in each pair < 0.1"
< 1.5" total length to avoid ISI and crosstalk
as short as possible
< 1.5" total length, delta in each pair < 0.1"
< 1.5" total length to avoid ISI and crosstalk
as short as possible
Trace lengths within each byte lane should not have a delta of more than 15-20ps (0.1" - .13").
Trace lengths between byte lanes should not have a delta of more than 60-70ps (0.4" - 0.47")
Trace lengths between byte lanes should not have a delta of more than 60-70ps (0.4" - 0.47")
All location are from 651 to 660
32/42LD570-ZB
DDR0_DQS0
DDR0_DQS1
DDR0_DQS1B
DDR0_DQS1B
DDR0_DQS0B
DDR1_DQS0
DDR1_DQS1
DDR1_DQS1B
DDR1_DQS1B
DDR1_DQS0B
DDR0_DM0
DDR0_DM1
DDR0_DM1
DDR1_DM1
DDR1_DM0
DDR01_RASB
DDR01_CASB
DDR01_WEB
DDR01_CASB
DDR01_WEB
DDR1_A6
DDR01_A8
DDR01_A9
DDR01_A10
DDR01_A9
DDR01_A10
DDR01_A0
DDR1_A4
DDR01_A7
DDR01_A11
DDR0_A4
DDR01_BA0
DDR01_A12
DDR01_BA1
DDR0_CLKB
DDR1_CLK
DDR1_CLKB
DDR1_CLK
DDR1_CLKB
DDR0_CLK
DDR01_BA2
DDR01_ODT
DDR0_A5
DDR0_A6
DDR0_A6
DDR01_A1
DDR01_A2
DDR01_A3
DDR01_A2
DDR01_A3
DDR1_A5
DDR0_VREF0
DDR0_DQ2
DDR0_DQ3
DDR0_DQ4
DDR0_DQ5
DDR0_DQ6
DDR0_DQ7
DDR0_DQ8
DDR0_DQ9
DDR0_DQ10
DDR0_DQ3
DDR0_DQ4
DDR0_DQ5
DDR0_DQ6
DDR0_DQ7
DDR0_DQ8
DDR0_DQ9
DDR0_DQ10
DDR0_DQ0
DDR0_DQ11
DDR0_DQ12
DDR0_DQ13
DDR0_DQ14
DDR0_DQ15
DDR0_DQ12
DDR0_DQ13
DDR0_DQ14
DDR0_DQ15
DDR0_DQ1
DDR1_VREF0
DDR01_A13
DDR1_DQ0
DDR1_DQ1
DDR1_DQ2
DDR1_DQ3
DDR1_DQ4
DDR1_DQ5
DDR1_DQ6
DDR1_DQ7
DDR1_DQ8
DDR1_DQ9
DDR1_DQ10
DDR1_DQ11
DDR1_DQ12
DDR1_DQ13
DDR1_DQ14
DDR1_DQ15
DDR1_DQ1
DDR1_DQ2
DDR1_DQ3
DDR1_DQ4
DDR1_DQ5
DDR1_DQ6
DDR1_DQ7
DDR1_DQ8
DDR1_DQ9
DDR1_DQ10
DDR1_DQ11
DDR1_DQ12
DDR1_DQ13
DDR1_DQ14
DDR1_DQ15
DDR01_BA[2:0]
DDR0_A[6:4]
DDR1_A[6:4]
DDR01_A[13:7]
DDR01_A[3:0]
DDR0_DQ[15:0]
DDR1_DQ[15:0]
DDR_VREF0
DDR_VREF1
D1V8_DDR
DDR1_DQS0
[18]
DDR1_DQS0b
[18]
DDR1_DQS1
[18]
DDR1_DQS1b
[18]
DDR0_DQS0
[18]
DDR0_DQS0b
[18]
DDR0_DQS1
[18]
DDR0_DQS1b
[18]
DDR0_DQ[15:0]
[18]
DDR1_DQ[15:0]
[18]
DDR1_DM0 [18]
DDR1_DM1 [18]
DDR1_DM1 [18]
DDR0_CLK
[18]
DDR0_CLKb
[18]
DDR1_CLK
[18]
DDR1_CLKb
[18]
DDR0_DM0 [18]
DDR0_DM1 [18]
DDR0_DM1 [18]
DDR01_RASb
[18]
DDR01_CASb
[18]
DDR01_WEb
[18]
DDR01_CKE
[18]
DDR01_ODT
[18]
DDR01_A[3:0]
[18]
DDR0_A[6:4]
[18]
DDR1_A[6:4]
[18]
DDR01_A[13:7]
[18]
DDR01_BA[2:0]
[18]
C654
471p/50V/1005
C654
471p/50V/1005
32Bit
DDR
SDRAM
DDR
SDRAM
U211R
BCM3556FKFSB1G
BCM3556FKFSB1G
BGA704_SKT_SMTBG_BCM3556
32Bit
DDR
SDRAM
DDR
SDRAM
U211R
BCM3556FKFSB1G
BCM3556FKFSB1G
BGA704_SKT_SMTBG_BCM3556
DDR01_A00
B15
DDR01_A01
E14
DDR01_A02
A15
DDR01_A03
D15
DDR0_A04
E13
DDR0_A05
E12
DDR0_A06
F13
DDR01_A07
C14
DDR01_A08
F14
DDR01_A09
B14
DDR01_A10
D14
DDR01_A11
C13
DDR01_A12
D13
DDR1_A04
F15
DDR1_A05
C15
DDR1_A06
D16
DDR01_BA0
F16
DDR01_BA1
B16
DDR01_BA2
E15
DDR0_DQ00
A8
DDR0_DQ01
B11
DDR0_DQ02
B8
DDR0_DQ03
D11
DDR0_DQ04
E11
DDR0_DQ05
C8
DDR0_DQ06
C11
DDR0_DQ07
C9
DDR0_DQ08
D8
DDR0_DQ09
E10
DDR0_DQ10
E9
DDR0_DQ11
F11
DDR0_DQ12
F12
DDR0_DQ13
E8
DDR0_DQ14
D10
DDR0_DQ15
F8
DDR1_DQ00
C18
DDR1_DQ01
C20
DDR1_DQ02
A18
DDR1_DQ03
B21
DDR1_DQ04
C21
DDR1_DQ05
B18
DDR1_DQ06
B20
DDR1_DQ07
D18
DDR1_DQ08
E18
DDR1_DQ09
D21
DDR1_DQ10
F18
DDR1_DQ11
E20
DDR1_DQ12
A22
DDR1_DQ13
F17
DDR1_DQ14
B22
DDR1_DQ15
E17
DDR0_DQS0
B10
DDR0_DQS0b
B9
DDR0_DQS1
F10
DDR0_DQS1b
F9
DDR1_DQS0
B19
DDR1_DQS0b
C19
DDR1_DQS1
E19
DDR1_DQS1b
D19
DDR0_DM0
A10
DDR0_DM1
C10
DDR1_DM0
A20
DDR1_DM1
F19
DDR01_RASb
C16
DDR01_CASb
A17
DDR01_WEb
C17
DDR0_CLK
B12
DDR0_CLKb
C12
DDR1_CLK
A13
DDR1_CLKb
A12
DDR01_CKE
B17
DDR01_ODT
E16
DDR_VREF0
A7
DDR_VREF1
A23
DDR_COMP
C22
DDR01_A13
B13
DDR_VDDP1P8
C7
DDR_VDDP1P8
D22
C653
105p/6.3V/1005
C653
105p/6.3V/1005
C651
105p/6.3V/1005
C651
105p/6.3V/1005
R651
241/F/1005
R651
241/F/1005
C652
471p/50V/1005
C652
471p/50V/1005
R652
220/1005
R652
220/1005
5
5
4
4
3
3
2
2
1
1
D
D
C
C
B
B
A
A
Hynix : H5PS1G63EFR-G7C
This board is laid out to support two 64Mx16.
The BOM currently supplies two 64Mx16 parts of DDR2-800, because the 2Gb parts are
extremely expensive.
The BOM currently supplies two 64Mx16 parts of DDR2-800, because the 2Gb parts are
extremely expensive.
Bcm3556 DDR2 Memory Controller supports up to 1GB memory space of DDR2-800 SDRAM.
All location are from 661 to 700
32/42LD570-ZB
DDR01_CASb
DDR01_RASb
DDR01_WEb
DDR01_A7
DDR01_A8
DDR01_A9
DDR01_A10
DDR01_A11
DDR01_A12
DDR01_A13
DDR01_A8
DDR01_A9
DDR01_A10
DDR01_A11
DDR01_A12
DDR01_A13
DDR01_A1
DDR01_A2
DDR01_A3
DDR01_A2
DDR01_A3
DDR01_A0
DDR0_A4
DDR0_A5
DDR0_A6
DDR0_A5
DDR0_A6
DDR0_DM1
DDR0_DM0
DDR01_BA0
DDR01_BA1
DDR01_BA2
DDR01_BA1
DDR01_BA2
DDR0_DQS0
DDR0_DQS0b
DDR0_DQS0b
DDR01_CKE
DDR0_CLK
DDR0_CLKb
DDR0_CLK
DDR0_CLKb
DDR01_ODT
DDR0_DQS1
DDR0_DQS1b
DDR0_DQS1b
DDR1_CLK
DDR1_CLKb
DDR1_CLKb
DDR01_CASb
DDR01_RASb
DDR01_WEb
DDR1_DM1
DDR1_DM0
DDR01_A7
DDR01_A8
DDR01_A9
DDR01_A10
DDR01_A11
DDR01_A12
DDR01_A8
DDR01_A9
DDR01_A10
DDR01_A11
DDR01_A12
DDR1_A4
DDR1_A5
DDR1_A6
DDR1_A5
DDR1_A6
DDR01_A1
DDR01_A2
DDR01_A3
DDR01_A2
DDR01_A3
DDR01_A0
DDR01_A13
DDR01_ODT
DDR01_BA0
DDR01_BA1
DDR01_BA2
DDR01_BA1
DDR01_BA2
DDR01_CKE
DDR1_DQS1
DDR1_DQS1b
DDR1_DQS1b
DDR1_DQS0
DDR1_DQS0b
DDR1_DQS0b
DDR0_A[6:4]
DDR1_A[6:4]
DDR01_A[13:7]
DDR0_DQ[15:0]
DDR1_DQ[15:0]
DDR01_A[3:0]
DDR01_BA[2:0]
DDR0_DQ0
DDR0_DQ1
DDR0_DQ2
DDR0_DQ3
DDR0_DQ4
DDR0_DQ5
DDR0_DQ6
DDR0_DQ7
DDR0_DQ8
DDR0_DQ14
DDR0_DQ10
DDR0_DQ11
DDR0_DQ12
DDR0_DQ15
DDR0_DQ9
DDR0_DQ13
DDR0_DQ1
DDR0_DQ2
DDR0_DQ3
DDR0_DQ4
DDR0_DQ5
DDR0_DQ6
DDR0_DQ7
DDR0_DQ8
DDR0_DQ14
DDR0_DQ10
DDR0_DQ11
DDR0_DQ12
DDR0_DQ15
DDR0_DQ9
DDR0_DQ13
DDR1_DQ1
DDR1_DQ0
DDR1_DQ2
DDR1_DQ3
DDR1_DQ4
DDR1_DQ5
DDR1_DQ6
DDR1_DQ7
DDR1_DQ8
DDR1_DQ9
DDR1_DQ10
DDR1_DQ11
DDR1_DQ14
DDR1_DQ15
DDR1_DQ12
DDR1_DQ13
DDR1_DQ3
DDR1_DQ4
DDR1_DQ5
DDR1_DQ6
DDR1_DQ7
DDR1_DQ8
DDR1_DQ9
DDR1_DQ10
DDR1_DQ11
DDR1_DQ14
DDR1_DQ15
DDR1_DQ12
DDR1_DQ13
DDR01_A10
DDR01_A9
DDR01_A12
DDR01_A7
DDR01_WEb
DDR1_A6
DDR01_RASb
DDR01_BA2
DDR01_RASb
DDR01_BA2
DDR0_A6
DDR01_A8
DDR01_BA1
DDR01_BA1
DDR1_A5
DDR01_A1
DDR1_A4
DDR01_A11
DDR01_CASb
DDR01_A13
DDR01_A0
DDR01_A2
DDR01_A3
DDR01_A3
DDR0_A4
DDR01_ODT
DDR01_BA0
DDR01_BA0
DDR0_A5
DDR01_CKE
DDR_VTT
DDR_VREF0
DDR_VREF1
D1V8_DDR
D1V8_DDR
D1V8_DDR
D1V8_DDR
DDR1_DQS0
[17]
DDR1_DQS0b
[17]
DDR1_DQS1
[17]
DDR1_DQS1b
[17]
DDR0_DQS0
[17]
DDR0_DQS0b
[17]
DDR0_DQS1
[17]
DDR0_DQS1b
[17]
DDR0_DQ[15:0]
[17]
DDR1_DQ[15:0]
[17]
DDR0_DM0
[17]
DDR0_DM1
[17]
DDR1_DM0
[17]
DDR1_DM1
[17]
DDR01_RASb
[17]
DDR01_CASb
[17]
DDR01_WEb
[17]
DDR0_CLK
[17]
DDR0_CLKb
[17]
DDR1_CLK
[17]
DDR1_CLKb
[17]
DDR01_CKE
[17]
DDR01_ODT
[17]
DDR01_BA[2:0]
[17]
DDR01_A[13:7]
[17]
DDR1_A[6:4]
[17]
DDR0_A[6:4]
[17]
DDR01_A[3:0]
[17]
CD698
471p/50V/1005
CD698
471p/50V/1005
CD675
104p/16V/1005
CD675
104p/16V/1005
CD693
104p/16V/1005
CD693
104p/16V/1005
CD670
104p/16V/1005
CD670
104p/16V/1005
CD696
104p/16V/1005
CD696
104p/16V/1005
CD661
226P/6.3V/2012
CD661
226P/6.3V/2012
CD695
104p/16V/1005
CD695
104p/16V/1005
CD676
104p/16V/1005
CD676
104p/16V/1005
CD691
104p/16V/1005
CD691
104p/16V/1005
CD682
104p/16V/1005
CD682
104p/16V/1005
CD683
104p/16V/1005
CD683
104p/16V/1005
CD679
104p/16V/1005
CD679
104p/16V/1005
CD688
104p/16V/1005
CD688
104p/16V/1005
CD680
471p/50V/1005
CD680
471p/50V/1005
CD668
104p/16V/1005
CD668
104p/16V/1005
CD687
104p/16V/1005
CD687
104p/16V/1005
RD661
101/1005
RD661
101/1005
CD665
104p/16V/1005
CD665
104p/16V/1005
PRD662
620*4/1005
PRD662
620*4/1005
1
8
2
7
3
6
4
5
DDR2
1Gb
UD661
H5PS1G63EFR-G7C
H5PS1G63EFR-G7C
DDR2
1Gb
UD661
H5PS1G63EFR-G7C
H5PS1G63EFR-G7C
VDD
A1
NC
A2
VSS
A3
VSSQ
A7
UDQS/NU
A8
VDDQ
A9
DQ14
B1
VSSQ
B2
UDM
B3
UDQS
B7
VSSQ
B8
DQ15
B9
VDDQ
C1
DQ9
C2
VDDQ
C3
VDDQ
C7
DQ8
C8
VDDQ
C9
DQ12
D1
VSSQ
D2
DQ11
D3
DQ10
D7
VSSQ
D8
DQ13
D9
VDD
E1
NC
E2
VSS
E3
VSSQ
E7
LDQS/NU
E8
VDDQ
E9
DQ6
F1
VSSQ
F2
LDM
F3
LDQS
F7
VSSQ
F8
DQ7
F9
VDDQ
G1
DQ1
G2
VDDQ
G3
VDDQ
G7
DQ0
G8
VDDQ
G9
DQ4
H1
VSSQ
H2
DQ3
H3
DQ2
H7
VSSQ
H8
DQ5
H9
VDDL
J1
VREF
J2
VSS
J3
VSSDL
J7
CK
J8
VDD
J9
CKE
K2
WE
K3
RAS
K7
CK
K8
ODT
K9
RFU/BA2
L1
BA0
L2
BA1
L3
CAS
L7
CS
L8
A10
M2
A1
M3
A2
M7
A0
M8
VDD
M9
VSS
N1
A3
N2
A5
N3
A6
N7
A4
N8
A7
P2
A9
P3
A11
P7
A8
P8
VSS
P9
VDD
R1
A12
R2
RFU/A14
R3
RFU/A15
R7
RFU/A13
R8
CD684
226P/6.3V/2012
CD684
226P/6.3V/2012
CD664
104p/16V/1005
CD664
104p/16V/1005
CD681
104p/16V/1005
CD681
104p/16V/1005
CD671
104p/16V/1005
CD671
104p/16V/1005
DDR2
1Gb
UD662
H5PS1G63EFR-G7C
H5PS1G63EFR-G7C
DDR2
1Gb
UD662
H5PS1G63EFR-G7C
H5PS1G63EFR-G7C
VDD
A1
NC
A2
VSS
A3
VSSQ
A7
UDQS/NU
A8
VDDQ
A9
DQ14
B1
VSSQ
B2
UDM
B3
UDQS
B7
VSSQ
B8
DQ15
B9
VDDQ
C1
DQ9
C2
VDDQ
C3
VDDQ
C7
DQ8
C8
VDDQ
C9
DQ12
D1
VSSQ
D2
DQ11
D3
DQ10
D7
VSSQ
D8
DQ13
D9
VDD
E1
NC
E2
VSS
E3
VSSQ
E7
LDQS/NU
E8
VDDQ
E9
DQ6
F1
VSSQ
F2
LDM
F3
LDQS
F7
VSSQ
F8
DQ7
F9
VDDQ
G1
DQ1
G2
VDDQ
G3
VDDQ
G7
DQ0
G8
VDDQ
G9
DQ4
H1
VSSQ
H2
DQ3
H3
DQ2
H7
VSSQ
H8
DQ5
H9
VDDL
J1
VREF
J2
VSS
J3
VSSDL
J7
CK
J8
VDD
J9
CKE
K2
WE
K3
RAS
K7
CK
K8
ODT
K9
RFU/BA2
L1
BA0
L2
BA1
L3
CAS
L7
CS
L8
A10
M2
A1
M3
A2
M7
A0
M8
VDD
M9
VSS
N1
A3
N2
A5
N3
A6
N7
A4
N8
A7
P2
A9
P3
A11
P7
A8
P8
VSS
P9
VDD
R1
A12
R2
RFU/A14
R3
RFU/A15
R7
RFU/A13
R8
CD685
226P/6.3V/2012
CD685
226P/6.3V/2012
CD677
104p/16V/1005
CD677
104p/16V/1005
PRD663
620*4/1005
PRD663
620*4/1005
1
8
2
7
3
6
4
5
CD678
104p/16V/1005
CD678
104p/16V/1005
R662
620/1005
R662
620/1005
CD697
104p/16V/1005
CD697
104p/16V/1005
CD686
104p/16V/1005
CD686
104p/16V/1005
CD673
104p/16V/1005
CD673
104p/16V/1005
CD689
104p/16V/1005
CD689
104p/16V/1005
RD664
101/1005
101/1005
RD664
101/1005
101/1005
CD662
226P/6.3V/2012
CD662
226P/6.3V/2012
CD666
104p/16V/1005
CD666
104p/16V/1005
CD663
104p/16V/1005
CD663
104p/16V/1005
PRD664
620*4/1005
PRD664
620*4/1005
1
8
2
7
3
6
4
5
CD690
104p/16V/1005
CD690
104p/16V/1005
PRD666
620*4/1005
PRD666
620*4/1005
1
8
2
7
3
6
4
5
CD694
104p/16V/1005
CD694
104p/16V/1005
CD667
104p/16V/1005
CD667
104p/16V/1005
PRD661
620*4/1005
PRD661
620*4/1005
1
8
2
7
3
6
4
5
RD663
620/1005
RD663
620/1005
CD692
104p/16V/1005
CD692
104p/16V/1005
PRD665
620*4/1005
PRD665
620*4/1005
1
8
2
7
3
6
4
5
CD672
104p/16V/1005
CD672
104p/16V/1005
CD674
104p/16V/1005
CD674
104p/16V/1005
CD669
104p/16V/1005
CD669
104p/16V/1005
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