Read LG 27LS5400 / 27LS540T (CHASSIS:LD02M) Service Manual online
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
B-MBA1
B-MBA0
B-MA5
C1219
0.1uF
B-MA6
A-MDQU3
B-MA1
B-MDQU2
C1245
0.1uF
AVDD_DDR0
R1226
240
1%
B-MDQU5
B-MVREFDQ
A-MA8
B-MVREFDQ
A-MVREFDQ
B-MDQL3
A-MDQU6
B-MDQL0
A-MDMU
A-MVREFCA
A-MDML
B-MA9
B-MA8
A-MA6
B-MDQSU
B-MBA2
B-MBA1
+1.5V_DDR
B-MA14
A-MDQL1
A-MDQU5
B-MVREFCA
A-MDQL0
B-MDQU5
A-MDQU2
R1236
56
1%
B-MCK
AVDD_DDR0
B-MA10
A-MDQL3
A-MDQL7
A-MA10
C1235
0.1uF
B-MDQL1
B-MA14
B-MDQU6
A-MA14
B-MDQU3
A-MA3
A-MRESETB
C1209
0.01uF
50V
AVDD_DDR0
B-MDQSU
B-MA11
B-MA12
C1205
10uF
A-MDQL3
A-MDQSL
A-MA4
A-MA4
C1206
0.1uF
C1236
0.1uF
B-MA2
A-MBA2
C1228
0.1uF
C1202
1000pF
A-MRASB
B-MDQSLB
B-MDQL2
A-MBA1
C1201
0.1uF
B-MA5
C1204
1000pF
B-MRESETB
B-MDQL6
A-MDQU5
A-MDQU7
B-MA0
A-MA0
B-MCKB
A-MA1
AVDD_DDR0
B-MDQL1
B-MODT
A-MDQSLB
A-MDQSU
B-MDQU7
A-MODT
B-MCKB
C1239
0.1uF
A-MDQU1
B-MDMU
A-MA2
C1229
0.1uF
A-MDQU3
A-MDQSUB
A-MCASB
B-MVREFCA
B-MDQU1
A-MA6
R1202
1K
1%
B-MDQL0
C1241
0.1uF
A-MWEB
A-MDQL0
A-MDQL2
A-MA10
B-MDML
B-MA7
B-MA7
B-MA0
A-MDQL5
AVDD_DDR0
B-MCKE
A-MDQSL
B-MDQL5
B-MDQSL
B-MDQL7
B-MDQU2
B-MDML
B-MA1
C1251
10uF
OPT
C1233
0.1uF
A-MCKB
C1248
0.1uF
R1203
240
1%
AVDD_DDR0
A-MDQL1
B-MWEB
C1247
1000pF
C1207
0.1uF
C1240
0.01uF
50V
B-MDQSUB
C1211
0.1uF
B-MA2
C1250
0.1uF
B-MA9
A-MCK
C1224
0.1uF
C1215
0.1uF
A-MA9
B-MDQU3
A-MA2
A-MA14
A-MA13
R1224
1K
1%
A-MA7
A-MDMU
A-MDQU0
A-MVREFCA
A-MA12
A-MA5
A-MDQL6
C1234
0.1uF
B-MDQU1
C1238
0.1uF
A-MA5
A-MDQU7
A-MRASB
B-MCASB
B-MRESETB
A-MA9
B-MBA0
A-MCKE
R1232
10K
B-MA13
A-MA13
C1243
0.1uF
C1227
0.1uF
R1231
10K
10K
AVDD_DDR0
B-MA3
B-MDQL7
B-MDQSLB
AVDD_DDR0
A-MDQL2
C1212
0.1uF
B-MDQU6
A-MCK
A-MDQL7
A-MA1
C1213
0.1uF
B-MDQL4
R1205
1K
1%
C1208
0.1uF
A-MDQSLB
C1249
1000pF
A-MBA2
B-MDQSL
A-MA3
A-MWEB
B-MDQL2
C1237
0.1uF
C1214
0.1uF
A-MA8
B-MDQU0
A-MDML
B-MBA2
C1216
0.1uF
B-MDQL3
B-MODT
A-MDQU2
B-MDMU
A-MDQU1
C1242
0.1uF
A-MDQL4
B-MA8
B-MCK
B-MDQL4
R1238
56
1%
B-MDQU4
R1227
1K
1%
B-MRASB
B-MA13
B-MDQSUB
C1230
0.1uF
A-MDQL5
A-MDQU4
A-MDQSUB
C1231
0.1uF
R1225
1K
1%
A-MDQU4
B-MDQL6
C1217
0.1uF
A-MCKE
B-MDQU0
A-MDQU6
A-MA11
A-MBA0
R1204
1K
1%
C1222
0.1uF
A-MDQL4
B-MA4
B-MCASB
A-MCKB
A-MRESETB
A-MBA1
B-MA10
B-MA3
R1201
1K
1%
A-MA11
R1228
1K
1%
B-MA4
C1221
0.1uF
R1237
56
1%
B-MCKE
B-MDQU7
B-MDQU4
A-MVREFDQ
B-MA11
A-MDQU0
C1223
0.1uF
C1220
0.1uF
A-MBA0
AVDD_DDR0
A-MCASB
A-MA7
A-MDQSU
C1232
0.1uF
C1203
0.1uF
B-MA6
B-MWEB
A-MA0
B-MRASB
R1235
56
1%
B-MA12
C1210
0.1uF
C1244
0.1uF
A-MA12
B-MDQL5
A-MODT
C1218
0.1uF
A-MDQL6
H5TQ1G63DFR-PBC
IC1201
1G DDR(Hynix)
EAN61829001
A0
N3
A1
P7
A2
P3
A3
N2
A4
P8
A5
P2
A6
R8
A7
R2
A8
T8
A9
R3
A10/AP
L7
A11
R7
A12/BC
N7
A13
T3
A15
M7
BA0
M2
BA1
N8
BA2
M3
CK
J7
CK
K7
CKE
K9
CS
L2
ODT
K1
RAS
J3
CAS
K3
WE
L3
RESET
T2
DQSL
F3
DQSL
G3
DQSU
C7
DQSU
B7
DML
E7
DMU
D3
DQL0
E3
DQL1
F7
DQL2
F2
DQL3
F8
DQL4
H3
DQL5
H8
DQL6
G2
DQL7
H7
DQU0
D7
DQU1
C3
DQU2
C8
DQU3
C2
DQU4
A7
DQU5
A2
DQU6
B8
DQU7
A3
VREFCA
M8
VREFDQ
H1
ZQ
L8
VDD_1
B2
VDD_2
D9
VDD_3
G7
VDD_4
K2
VDD_5
K8
VDD_6
N1
VDD_7
N9
VDD_8
R1
VDD_9
R9
VDDQ_1
A1
VDDQ_2
A8
VDDQ_3
C1
VDDQ_4
C9
VDDQ_5
D2
VDDQ_6
E9
VDDQ_7
F1
VDDQ_8
H2
VDDQ_9
H9
NC_1
J1
NC_2
J9
NC_3
L1
NC_4
L9
NC_6
T7
VSS_1
A9
VSS_2
B3
VSS_3
E1
VSS_4
G8
VSS_5
J2
VSS_6
J8
VSS_7
M1
VSS_8
M9
VSS_9
P1
VSS_10
P9
VSS_11
T1
VSS_12
T9
VSSQ_1
B1
VSSQ_2
B9
VSSQ_3
D1
VSSQ_4
D8
VSSQ_5
E2
VSSQ_6
E8
VSSQ_7
F9
VSSQ_8
G1
VSSQ_9
G9
H5TQ1G63DFR-PBC
IC1202
1G DDR(Hynix)
EAN61829001
A0
N3
A1
P7
A2
P3
A3
N2
A4
P8
A5
P2
A6
R8
A7
R2
A8
T8
A9
R3
A10/AP
L7
A11
R7
A12/BC
N7
A13
T3
A15
M7
BA0
M2
BA1
N8
BA2
M3
CK
J7
CK
K7
CKE
K9
CS
L2
ODT
K1
RAS
J3
CAS
K3
WE
L3
RESET
T2
DQSL
F3
DQSL
G3
DQSU
C7
DQSU
B7
DML
E7
DMU
D3
DQL0
E3
DQL1
F7
DQL2
F2
DQL3
F8
DQL4
H3
DQL5
H8
DQL6
G2
DQL7
H7
DQU0
D7
DQU1
C3
DQU2
C8
DQU3
C2
DQU4
A7
DQU5
A2
DQU6
B8
DQU7
A3
VREFCA
M8
VREFDQ
H1
ZQ
L8
VDD_1
B2
VDD_2
D9
VDD_3
G7
VDD_4
K2
VDD_5
K8
VDD_6
N1
VDD_7
N9
VDD_8
R1
VDD_9
R9
VDDQ_1
A1
VDDQ_2
A8
VDDQ_3
C1
VDDQ_4
C9
VDDQ_5
D2
VDDQ_6
E9
VDDQ_7
F1
VDDQ_8
H2
VDDQ_9
H9
NC_1
J1
NC_2
J9
NC_3
L1
NC_4
L9
NC_6
T7
VSS_1
A9
VSS_2
B3
VSS_3
E1
VSS_4
G8
VSS_5
J2
VSS_6
J8
VSS_7
M1
VSS_8
M9
VSS_9
P1
VSS_10
P9
VSS_11
T1
VSS_12
T9
VSSQ_1
B1
VSSQ_2
B9
VSSQ_3
D1
VSSQ_4
D8
VSSQ_5
E2
VSSQ_6
E8
VSSQ_7
F9
VSSQ_8
G1
VSSQ_9
G9
R1239
0
0
1/10W
5%
5%
IC101
LGE2111A-T8
EU/BRA/AUS
A_DDR3_A[0]
A11
A_DDR3_A[1]
C14
A_DDR3_A[2]
B11
A_DDR3_A[3]
F12
A_DDR3_A[4]
C15
A_DDR3_A[5]
E12
A_DDR3_A[6]
A14
A_DDR3_A[7]
D11
A_DDR3_A[8]
B14
A_DDR3_A[9]
D12
A_DDR3_A[10]
C16
A_DDR3_A[11]
C13
A_DDR3_A[12]
A15
A_DDR3_A[13]
E11
A_DDR3_A[14]
B13
A_DDR3_BA[0]
F13
A_DDR3_BA[1]
B15
A_DDR3_BA[2]
E13
A_DDR3_MCLK
C17
A_DDR3_MCLKZ
A17
A_DDR3_MCLKE
B16
A_DDR3_ODT
E14
A_DDR3_RASZ
B12
A_DDR3_CASZ
A12
A_DDR3_WEZ
C12
A_DDR3_RESET
F11
A_DDR3_DQSL
B19
A_DDR3_DQSLB
C18
A_DDR3_DQSU
B18
A_DDR3_DQSUB
A18
A_DDR3_DQML
E15
A_DDR3_DQMU
A21
A_DDR3_DQL[0]
D17
A_DDR3_DQL[1]
G15
A_DDR3_DQL[2]
B21
A_DDR3_DQL[3]
F15
A_DDR3_DQL[4]
B22
A_DDR3_DQL[5]
F14
A_DDR3_DQL[6]
A22
A_DDR3_DQL[7]
D15
A_DDR3_DQU[0]
G16
A_DDR3_DQU[1]
B20
A_DDR3_DQU[2]
F16
A_DDR3_DQU[3]
C21
A_DDR3_DQU[4]
E16
A_DDR3_DQU[5]
A20
A_DDR3_DQU[6]
D16
A_DDR3_DQU[7]
C20
B_DDR3_A[0]
B23
B_DDR3_A[1]
D25
B_DDR3_A[2]
F22
B_DDR3_A[3]
G22
B_DDR3_A[4]
E24
B_DDR3_A[5]
F21
B_DDR3_A[6]
E23
B_DDR3_A[7]
D22
B_DDR3_A[8]
D24
B_DDR3_A[9]
D21
B_DDR3_A[10]
C24
B_DDR3_A[11]
C25
B_DDR3_A[12]
F23
B_DDR3_A[13]
E21
B_DDR3_A[14]
D23
B_DDR3_BA[0]
G20
B_DDR3_BA[1]
F24
B_DDR3_BA[2]
F20
B_DDR3_MCLK
G25
B_DDR3_MCLKZ
G23
B_DDR3_MCLKE
F25
B_DDR3_ODT
D20
B_DDR3_RASZ
B25
B_DDR3_CASZ
B24
B_DDR3_WEZ
A24
B_DDR3_RESET
E20
B_DDR3_DQSL
K24
B_DDR3_DQSLB
K25
B_DDR3_DQSU
J21
B_DDR3_DQSUB
J20
B_DDR3_DQML
H24
B_DDR3_DQMU
L20
B_DDR3_DQL[0]
L23
B_DDR3_DQL[1]
J24
B_DDR3_DQL[2]
L24
B_DDR3_DQL[3]
J23
B_DDR3_DQL[4]
M24
B_DDR3_DQL[5]
H23
B_DDR3_DQL[6]
M23
B_DDR3_DQL[7]
K23
B_DDR3_DQU[0]
G21
B_DDR3_DQU[1]
L22
B_DDR3_DQU[2]
H22
B_DDR3_DQU[3]
K20
B_DDR3_DQU[4]
H20
B_DDR3_DQU[5]
L21
B_DDR3_DQU[6]
H21
B_DDR3_DQU[7]
K21
H5TQ2G63BFR-PBC
IC1201-*2
2G DDR(Hynix)
A0
N3
A1
P7
A2
P3
A3
N2
A4
P8
A5
P2
A6
R8
A7
R2
A8
T8
A9
R3
A10/AP
L7
A11
R7
A12/BC
N7
A13
T3
A15
M7
BA0
M2
BA1
N8
BA2
M3
CK
J7
CK
K7
CKE
K9
CS
L2
ODT
K1
RAS
J3
CAS
K3
WE
L3
RESET
T2
DQSL
F3
DQSL
G3
DQSU
C7
DQSU
B7
DML
E7
DMU
D3
DQL0
E3
DQL1
F7
DQL2
F2
DQL3
F8
DQL4
H3
DQL5
H8
DQL6
G2
DQL7
H7
DQU0
D7
DQU1
C3
DQU2
C8
DQU3
C2
DQU4
A7
DQU5
A2
DQU6
B8
DQU7
A3
VREFCA
M8
VREFDQ
H1
ZQ
L8
VDD_1
B2
VDD_2
D9
VDD_3
G7
VDD_4
K2
VDD_5
K8
VDD_6
N1
VDD_7
N9
VDD_8
R1
VDD_9
R9
VDDQ_1
A1
VDDQ_2
A8
VDDQ_3
C1
VDDQ_4
C9
VDDQ_5
D2
VDDQ_6
E9
VDDQ_7
F1
VDDQ_8
H2
VDDQ_9
H9
NC_1
J1
NC_2
J9
NC_3
L1
NC_4
L9
NC_6
T7
VSS_1
A9
VSS_2
B3
VSS_3
E1
VSS_4
G8
VSS_5
J2
VSS_6
J8
VSS_7
M1
VSS_8
M9
VSS_9
P1
VSS_10
P9
VSS_11
T1
VSS_12
T9
VSSQ_1
B1
VSSQ_2
B9
VSSQ_3
D1
VSSQ_4
D8
VSSQ_5
E2
VSSQ_6
E8
VSSQ_7
F9
VSSQ_8
G1
VSSQ_9
G9
MT41J64M16JT-125:G
IC1202-*1
1G DDR(Micron)
A0
N3
A1
P7
A2
P3
A3
N2
A4
P8
A5
P2
A6
R8
A7
R2
A8
T8
A9
R3
A10/AP
L7
A11
R7
A12/BC
N7
NC_6
T3
A15
M7
BA0
M2
BA1
N8
BA2
M3
CK
J7
CK
K7
CKE
K9
CS
L2
ODT
K1
RAS
J3
CAS
K3
WE
L3
RESET
T2
DQSL
F3
DQSL
G3
DQSU
C7
DQSU
B7
DML
E7
DMU
D3
DQ0
E3
DQ1
F7
DQ2
F2
DQ3
F8
DQ4
H3
DQ5
H8
DQ6
G2
DQ7
H7
DQ8
D7
DQ9
C3
DQ10
C8
DQ11
C2
DQ12
A7
DQ13
A2
DQ14
B8
DQ15
A3
VREFCA
M8
VREFDQ
H1
ZQ
L8
VDD_1
B2
VDD_2
D9
VDD_3
G7
VDD_4
K2
VDD_5
K8
VDD_6
N1
VDD_7
N9
VDD_8
R1
VDD_9
R9
VDDQ_1
A1
VDDQ_2
A8
VDDQ_3
C1
VDDQ_4
C9
VDDQ_5
D2
VDDQ_6
E9
VDDQ_7
F1
VDDQ_8
H2
VDDQ_9
H9
NC_1
J1
NC_2
J9
NC_3
L1
NC_4
L9
NC_5
T7
VSS_1
A9
VSS_2
B3
VSS_3
E1
VSS_4
G8
VSS_5
J2
VSS_6
J8
VSS_7
M1
VSS_8
M9
VSS_9
P1
VSS_10
P9
VSS_11
T1
VSS_12
T9
VSSQ_1
B1
VSSQ_2
B9
VSSQ_3
D1
VSSQ_4
D8
VSSQ_5
E2
VSSQ_6
E8
VSSQ_7
F9
VSSQ_8
G1
VSSQ_9
G9
MT41J64M16JT-125:G
IC1201-*1
1G DDR(Micron)
A0
N3
A1
P7
A2
P3
A3
N2
A4
P8
A5
P2
A6
R8
A7
R2
A8
T8
A9
R3
A10/AP
L7
A11
R7
A12/BC
N7
NC_6
T3
A15
M7
BA0
M2
BA1
N8
BA2
M3
CK
J7
CK
K7
CKE
K9
CS
L2
ODT
K1
RAS
J3
CAS
K3
WE
L3
RESET
T2
DQSL
F3
DQSL
G3
DQSU
C7
DQSU
B7
DML
E7
DMU
D3
DQ0
E3
DQ1
F7
DQ2
F2
DQ3
F8
DQ4
H3
DQ5
H8
DQ6
G2
DQ7
H7
DQ8
D7
DQ9
C3
DQ10
C8
DQ11
C2
DQ12
A7
DQ13
A2
DQ14
B8
DQ15
A3
VREFCA
M8
VREFDQ
H1
ZQ
L8
VDD_1
B2
VDD_2
D9
VDD_3
G7
VDD_4
K2
VDD_5
K8
VDD_6
N1
VDD_7
N9
VDD_8
R1
VDD_9
R9
VDDQ_1
A1
VDDQ_2
A8
VDDQ_3
C1
VDDQ_4
C9
VDDQ_5
D2
VDDQ_6
E9
VDDQ_7
F1
VDDQ_8
H2
VDDQ_9
H9
NC_1
J1
NC_2
J9
NC_3
L1
NC_4
L9
NC_5
T7
VSS_1
A9
VSS_2
B3
VSS_3
E1
VSS_4
G8
VSS_5
J2
VSS_6
J8
VSS_7
M1
VSS_8
M9
VSS_9
P1
VSS_10
P9
VSS_11
T1
VSS_12
T9
VSSQ_1
B1
VSSQ_2
B9
VSSQ_3
D1
VSSQ_4
D8
VSSQ_5
E2
VSSQ_6
E8
VSSQ_7
F9
VSSQ_8
G1
VSSQ_9
G9
CLose to DDR3
DDR3 1.5V By CAP - Place these Caps near Memory
DDR3 1.5V By CAP - Place these Caps near Memory
Close to DDR Power Pin
CLose to Saturn7M IC
CLose to DDR3
CLose to Saturn7M IC
Close to DDR Power Pin
10 11
DDR MEMORY
DMxx52/Mxx52
Mxx32
EAX64559005
2012.05.23
Click on the first or last page to see other 27LS5400 / 27LS540T (CHASSIS:LD02M) service manuals if exist.